rework threads synchronization

add cpuid definitions
add new command parameter 'delay' to allow pausing between accesses
author contact updated

Makefile

@@ -51,8 +51,8 @@ endif
 
 #LFLAGS_LINUX += -Wl,--section-start=.pmbench_code_page=408000
 # uncomment below to compile-in multi-threaded benchmark
-CFLAGS_LINUX += -DPMB_THREAD=1 -pthread
-LFLAGS_LINUX += -pthread 
+#CFLAGS_LINUX += -DPMB_THREAD=1 -pthread
+#LFLAGS_LINUX += -pthread 
 # uncomment below to add XALLOC
 #CFLAGS_LINUX += -DXALLOC -I../xalloc
 #LFLAGS_LINUX += ../xalloc/libxalloc.a
@@ -64,8 +64,8 @@ LIBPATH_WINARGP := ../argpwin
 CFLAGS_WIN := -D_WIN32_WINNT=0x0501 -I$(INCPATH_WINARGP)
 LFLAGS_WIN := -lrpcrt4  -L$(LIBPATH_WINARGP)
 # uncomment below to compile-in multi-threaded benchmark
-CFLAGS_WIN += -DPMB_THREAD=1 -lpthread
-LFLAGS_WIN += -lpthread
+#CFLAGS_WIN += -DPMB_THREAD=1 -lpthread
+#LFLAGS_WIN += -lpthread
 # uncomment below to add XALLOC
 #CFLAGS_WIN += -DXALLOC -I../xalloc
 #LFLAGS_WIN += ../xalloc/xalloc.dll 

access.c

@@ -27,9 +27,7 @@
    POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
- * Written by: Jisoo Yang <[email protected]> 
- */
+/* Written by: Jisoo Yang <jisoo.yang (at) unlv.edu> */
 
 #include <stdlib.h>
 #include <stdio.h>
@@ -64,7 +62,6 @@ void atomic_dec(unsigned* pval) {
 /** 
  * NB. Using function pointer to 1) choose method easily and 2) avoid
  * possible compiler optimization around the function call.
- * Note: probably better writing in asm?
  */
 
 /*

access.h

@@ -29,9 +29,7 @@
    POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
- * Written by Jisoo Yang <[email protected]> 
- */
+/* Written by: Jisoo Yang <jisoo.yang (at) unlv.edu> */
 
 typedef struct access_fn_set {
     int (*warmup)(char* buf, size_t pfn);		// callback for warmup touch

cpuid.h

@@ -29,24 +29,7 @@
    POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
- * Written by: Jisoo Yang <[email protected]>
- */
-
-#if 0
-// below _sys_cpuid() is to be used when compiled with MSVC
-#include <intrin.h>
-static __inline 
-void _sys_cpuid(unsigned* a, unsigned* b, unsigned* c, unsigned* d)
-{
-    static const int A = 0, B = 1, C = 2, D = 3;
-    int r[4];
-
-    __cpuidex(r, *a, *c);
-
-    *a = r[A]; *b = r[B]; *c = r[C]; *d = r[D];
-}
-#endif
+/* Written by: Jisoo Yang <jisoo.yang (at) unlv.edu> */
 
 /* generic cpuid */
 static inline
@@ -57,30 +40,45 @@ void _sys_cpuid(unsigned* a, unsigned* b, unsigned* c, unsigned* d)
 	: "0"(*a), "2"(*c));
 }
 
-
+/* CPUID 02 leaflets as of Intel SDM Version 047 (December 2015) */
 #define __CPUID02_0x01_STR "ITLB: 32 entries for 4KB, 4-way\n"
 #define __CPUID02_0x02_STR "ITLB: 2 entries for 4MB, full\n"
 #define __CPUID02_0x03_STR "DTLB: 64 entries for 4KB, 4-way\n"
 #define __CPUID02_0x04_STR "DTLB: 8 entries for 4MB, 4-way\n"
+#define __CPUID02_0x05_STR "DTLB: 32 entries for 4MB, 4-way\n"
 #define __CPUID02_0x0B_STR "ITLB: 4 entries for 4MB, 4-way\n"
 #define __CPUID02_0x4F_STR "ITLB: 32 entries for 4KB\n"
 #define __CPUID02_0x50_STR "ITLB: 64 entries for 4KB and 2MB or 4MB\n"
 #define __CPUID02_0x51_STR "ITLB: 128 entries for 4KB and 2MB or 4MB\n"
 #define __CPUID02_0x52_STR "ITLB: 256 entries for 4KB and 2MB or 4MB\n"
+#define __CPUID02_0x55_STR "ITLB: 7 entries for 2MB or 4MB, full\n"
 #define __CPUID02_0x56_STR "DTLB0: 16 entries for 4MB, 4-way\n"
 #define __CPUID02_0x57_STR "DTLB0: 16 entries for 4KB, 4-way\n"
 #define __CPUID02_0x59_STR "DTLB0: 16 entries for 4MB, full\n"
 #define __CPUID02_0x5A_STR "DTLB0: 32 entries for 2MB or 4MB, 4-way\n"
 #define __CPUID02_0x5B_STR "DTLB: 64 entries for 4KB and 4MB\n"
 #define __CPUID02_0x5C_STR "DTLB: 128 entries for 4KB and 4MB\n"
 #define __CPUID02_0x5D_STR "DTLB: 256 entries for 4KB and 4MB\n"
+#define __CPUID02_0x61_STR "ITLB: 48 entries for 4KB, full \n"
+#define __CPUID02_0x63_STR "DTLB: 4 entries for 1GB, 4-way\n"
+#define __CPUID02_0x6A_STR "ITLB: 64 entries for 4KB, 8-way\n"
+#define __CPUID02_0x6B_STR "DTLB: 256 entries for 4KB, 8-way\n"
+#define __CPUID02_0x6C_STR "DTLB: 128 entries for 2MB or 4MB, 8-way\n"
+#define __CPUID02_0x6D_STR "DTLB: 16 entries for 1GB, full\n"
+#define __CPUID02_0x76_STR "ITLB: 8 entries for 2MB or 4MB, full\n"
+#define __CPUID02_0xA0_STR "DTLB: 32 entries for 4KB, full\n"
 #define __CPUID02_0xB0_STR "ITLB: 128 entries for 4KB, 4-way\n"
 #define __CPUID02_0xB1_STR "ITLB: 8 entries for 2MB, 4-way or 4 entries for 4MB, 4-way\n"
 #define __CPUID02_0xB2_STR "ITLB: 64 entries for 4KB, 4-way\n"
 #define __CPUID02_0xB3_STR "DTLB: 128 entries for 4KB, 4-way\n"
 #define __CPUID02_0xB4_STR "DTLB1: 256 entries for 4KB, 4-way\n"
+#define __CPUID02_0xB5_STR "ITLB: 64 entries for 4KB, 8-way\n"
+#define __CPUID02_0xB6_STR "ITLB: 128 entries for 4KB, 8-way\n"
 #define __CPUID02_0xBA_STR "DTLB1: 64 entries for 4KB, 4-way\n"
 #define __CPUID02_0xC0_STR "DTLB: 8 entries for 4KB and 4MB, 4-way\n"
+#define __CPUID02_0xC1_STR "STLB: 1024 entries for 4KB and 2MB, 8-way, shared 2nd level\n"
+#define __CPUID02_0xC2_STR "DTLB: 16 entries for 4KB and 2MB, 4-way\n"
+#define __CPUID02_0xC3_STR "STLB: 1536 entries for 4KB and 2MB, 6-way, shared 2nd level. Also 16 entries for 1GB, 4-way\n"
 #define __CPUID02_0xCA_STR "STLB: 512 entries for 4KB, 4-way, shared 2nd level\n"
 
 
@@ -91,11 +89,13 @@ void _sys_cpuid(unsigned* a, unsigned* b, unsigned* c, unsigned* d)
 #define __CPUID02_0x0C_STR "DCACHE: 16KB 1st, 32B line, 4-way\n"
 #define __CPUID02_0x0D_STR "DCACHE: 16KB 1st, 64B line, 4-way\n"
 #define __CPUID02_0x0E_STR "DCACHE: 24KB 1st, 64B line, 6-way\n"
+#define __CPUID02_0x1D_STR "CACHE: 128KB 2nd, 64B line, 2-way\n"
 #define __CPUID02_0x21_STR "CACHE: 256KB 2nd, 64B line, 8-way\n"
-#define __CPUID02_0x22_STR "CACHE: 512KB 3rd, 64B line, 4-way, 2-lines\n"
-#define __CPUID02_0x23_STR "CACHE: 1MB 3rd, 64B line, 8-way, 2-lines\n"
-#define __CPUID02_0x25_STR "CACHE: 2MB 3rd, 64B line, 8-way, 2-lines\n"
-#define __CPUID02_0x29_STR "CACHE: 4MB 3rd, 64B line, 8-way, 2-lines\n"
+#define __CPUID02_0x22_STR "CACHE: 512KB 3rd, 64B line, 4-way, 2-lines per sector\n"
+#define __CPUID02_0x23_STR "CACHE: 1MB 3rd, 64B line, 8-way, 2-lines per sector\n"
+#define __CPUID02_0x24_STR "CACHE: 1MB 2nd, 64B line, 16-way\n"
+#define __CPUID02_0x25_STR "CACHE: 2MB 3rd, 64B line, 8-way, 2-lines per sector\n"
+#define __CPUID02_0x29_STR "CACHE: 4MB 3rd, 64B line, 8-way, 2-lines per sector\n"
 #define __CPUID02_0x2C_STR "DCACHE: 32KB 1st, 64B line, 8-way\n"
 #define __CPUID02_0x30_STR "ICACHE: 32KB 1st, 64B line, 8-way\n"
 #define __CPUID02_0x40_STR "CACHE: No 2nd or 3rd level cache\n"
@@ -137,7 +137,6 @@ void _sys_cpuid(unsigned* a, unsigned* b, unsigned* c, unsigned* d)
 
 #define __CPUID02_0xD0_STR "CACHE: 512KB 3rd, 64B line, 4-way\n"
 #define __CPUID02_0xD1_STR "CACHE: 1MB 3rd, 64B line, 4-way\n"
-
 #define __CPUID02_0xD2_STR "CACHE: 2MB 3rd, 64B line, 4-way\n"
 #define __CPUID02_0xD6_STR "CACHE: 1MB 3rd, 64B line, 8-way\n"
 #define __CPUID02_0xD7_STR "CACHE: 2MB 3rd, 64B line, 8-way\n"
@@ -154,6 +153,10 @@ void _sys_cpuid(unsigned* a, unsigned* b, unsigned* c, unsigned* d)
 #define __CPUID02_0xEB_STR "CACHE: 18MB 3rd, 64B line, 24-way\n"
 #define __CPUID02_0xEC_STR "CACHE: 24MB 3rd, 64B line, 24-way\n"
 
+#define __CPUID02_0xF0_STR "PREFETCH: 64B prefetching\n"
+#define __CPUID02_0xF1_STR "PREFETCH: 128B prefetching\n"
+
+
 
 #define ___CPUID02_PRN(num) \
 case num: printf(__CPUID02_##num##_STR); break; 
@@ -163,25 +166,40 @@ ___CPUID02_PRN(0x01) \
 ___CPUID02_PRN(0x02) \
 ___CPUID02_PRN(0x03) \
 ___CPUID02_PRN(0x04) \
+___CPUID02_PRN(0x05) \
 ___CPUID02_PRN(0x0B) \
 ___CPUID02_PRN(0x4F) \
 ___CPUID02_PRN(0x50) \
 ___CPUID02_PRN(0x51) \
 ___CPUID02_PRN(0x52) \
+___CPUID02_PRN(0x55) \
 ___CPUID02_PRN(0x56) \
 ___CPUID02_PRN(0x57) \
 ___CPUID02_PRN(0x59) \
 ___CPUID02_PRN(0x5A) \
 ___CPUID02_PRN(0x5B) \
 ___CPUID02_PRN(0x5C) \
 ___CPUID02_PRN(0x5D) \
+___CPUID02_PRN(0x61) \
+___CPUID02_PRN(0x63) \
+___CPUID02_PRN(0x6A) \
+___CPUID02_PRN(0x6B) \
+___CPUID02_PRN(0x6C) \
+___CPUID02_PRN(0x6D) \
+___CPUID02_PRN(0x76) \
+___CPUID02_PRN(0xA0) \
 ___CPUID02_PRN(0xB0) \
 ___CPUID02_PRN(0xB1) \
 ___CPUID02_PRN(0xB2) \
 ___CPUID02_PRN(0xB3) \
 ___CPUID02_PRN(0xB4) \
+___CPUID02_PRN(0xB5) \
+___CPUID02_PRN(0xB6) \
 ___CPUID02_PRN(0xBA) \
 ___CPUID02_PRN(0xC0) \
+___CPUID02_PRN(0xC1) \
+___CPUID02_PRN(0xC2) \
+___CPUID02_PRN(0xC3) \
 ___CPUID02_PRN(0xCA) 
 
 #define CPUID02_CACHE_PRN() \
@@ -192,9 +210,11 @@ ___CPUID02_PRN(0x0A) \
 ___CPUID02_PRN(0x0C) \
 ___CPUID02_PRN(0x0D) \
 ___CPUID02_PRN(0x0E) \
+___CPUID02_PRN(0x1D) \
 ___CPUID02_PRN(0x21) \
 ___CPUID02_PRN(0x22) \
 ___CPUID02_PRN(0x23) \
+___CPUID02_PRN(0x24) \
 ___CPUID02_PRN(0x25) \
 ___CPUID02_PRN(0x29) \
 ___CPUID02_PRN(0x2C) \

debug.c

@@ -26,9 +26,8 @@
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
  */
-/*
- * Written by: Jisoo Yang <[email protected]>
- */
+
+/* Written by: Jisoo Yang <jisoo.yang (at) unlv.edu> */
 
 /*
  * this file contains debug/test code which is only compiled in when testing

pattern.c

@@ -27,9 +27,7 @@
    POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
- * Written by: Jisoo Yang <[email protected]> 
- */
+/* Written by: Jisoo Yang <jisoo.yang (at) unlv.edu> */
 
 #include <stdlib.h>
 #include <stdio.h>

pattern.h

@@ -28,9 +28,8 @@
    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
    POSSIBILITY OF SUCH DAMAGE.
  */
-/*
- * Written by: Jisoo Yang <[email protected]> 
- */
+
+/* Written by: Jisoo Yang <jisoo.yang (at) unlv.edu> */
 
 //#define USE_LONG_DOUBLE 1
 #ifdef USE_LONG_DOUBLE