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  • Tsinghua University
  • 22:47 (UTC +08:00)

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  1. XiangShan XiangShan Public

    Forked from OpenXiangShan/XiangShan

    Open-source high-performance RISC-V processor

    Scala

  2. mit-6.8540 mit-6.8540 Public

    Homework for course Distributed System(6.8540) in MIT

    Go

  3. Chisel-Cod-Lab Chisel-Cod-Lab Public

    Chisel version for Computer Organization and Design Lab

    Scala

  4. MipsGreatAgain-Soc MipsGreatAgain-Soc Public

    Forked from liu-hz18/MipsGreatAgain-Soc

    A light-weighted synthesizable 9-stage-pipelined MIPS processor with branch prediction and CP1(FPU) support.

    Verilog