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Merge branch 'qed-Add-support-for-new-multi-partitioning-modes'
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Sudarsana Reddy Kalluru says:

====================
qed*: Add support for new multi partitioning modes.

The patch series simplifies the multi function (MF) mode implementation of
qed/qede drivers, and adds support for new MF modes.

Please consider applying it to net-next branch.
====================

Signed-off-by: David S. Miller <[email protected]>
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@davem330
davem330 committed May 8, 2018
2 parents 3a443bd + cac6f69 commit db0aeb3
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Showing 17 changed files with 389 additions and 82 deletions.
61 changes: 57 additions & 4 deletions drivers/net/ethernet/qlogic/qed/qed.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -439,6 +439,59 @@ struct qed_fw_data {
u32 init_ops_size;
};

enum qed_mf_mode_bit {
/* Supports PF-classification based on tag */
QED_MF_OVLAN_CLSS,

/* Supports PF-classification based on MAC */
QED_MF_LLH_MAC_CLSS,

/* Supports PF-classification based on protocol type */
QED_MF_LLH_PROTO_CLSS,

/* Requires a default PF to be set */
QED_MF_NEED_DEF_PF,

/* Allow LL2 to multicast/broadcast */
QED_MF_LL2_NON_UNICAST,

/* Allow Cross-PF [& child VFs] Tx-switching */
QED_MF_INTER_PF_SWITCH,

/* Unified Fabtic Port support enabled */
QED_MF_UFP_SPECIFIC,

/* Disable Accelerated Receive Flow Steering (aRFS) */
QED_MF_DISABLE_ARFS,

/* Use vlan for steering */
QED_MF_8021Q_TAGGING,

/* Use stag for steering */
QED_MF_8021AD_TAGGING,

/* Allow DSCP to TC mapping */
QED_MF_DSCP_TO_TC_MAP,
};

enum qed_ufp_mode {
QED_UFP_MODE_ETS,
QED_UFP_MODE_VNIC_BW,
QED_UFP_MODE_UNKNOWN
};

enum qed_ufp_pri_type {
QED_UFP_PRI_OS,
QED_UFP_PRI_VNIC,
QED_UFP_PRI_UNKNOWN
};

struct qed_ufp_info {
enum qed_ufp_pri_type pri_type;
enum qed_ufp_mode mode;
u8 tc;
};

enum BAR_ID {
BAR_ID_0, /* used for GRC */
BAR_ID_1 /* Used for doorbells */
Expand Down Expand Up @@ -547,6 +600,8 @@ struct qed_hwfn {

struct qed_dcbx_info *p_dcbx_info;

struct qed_ufp_info ufp_info;

struct qed_dmae_info dmae_info;

/* QM init */
Expand Down Expand Up @@ -669,10 +724,8 @@ struct qed_dev {
u8 num_funcs_in_port;

u8 path_id;
enum qed_mf_mode mf_mode;
#define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)

unsigned long mf_bits;

int pcie_width;
int pcie_speed;
Expand Down
14 changes: 12 additions & 2 deletions drivers/net/ethernet/qlogic/qed/qed_dcbx.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -274,15 +274,16 @@ qed_dcbx_process_tlv(struct qed_hwfn *p_hwfn,
u32 pri_tc_tbl, int count, u8 dcbx_version)
{
enum dcbx_protocol_type type;
bool enable, ieee, eth_tlv;
u8 tc, priority_map;
bool enable, ieee;
u16 protocol_id;
int priority;
int i;

DP_VERBOSE(p_hwfn, QED_MSG_DCB, "Num APP entries = %d\n", count);

ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE);
eth_tlv = false;
/* Parse APP TLV */
for (i = 0; i < count; i++) {
protocol_id = QED_MFW_GET_FIELD(p_tbl[i].entry,
Expand All @@ -304,13 +305,22 @@ qed_dcbx_process_tlv(struct qed_hwfn *p_hwfn,
* indication, but we only got here if there was an
* app tlv for the protocol, so dcbx must be enabled.
*/
enable = !(type == DCBX_PROTOCOL_ETH);
if (type == DCBX_PROTOCOL_ETH) {
enable = false;
eth_tlv = true;
} else {
enable = true;
}

qed_dcbx_update_app_info(p_data, p_hwfn, enable,
priority, tc, type);
}
}

/* If Eth TLV is not detected, use UFP TC as default TC */
if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits) && !eth_tlv)
p_data->arr[DCBX_PROTOCOL_ETH].tc = p_hwfn->ufp_info.tc;

/* Update ramrod protocol data and hw_info fields
* with default info when corresponding APP TLV's are not detected.
* The enabled field has a different logic for ethernet as only for
Expand Down
113 changes: 78 additions & 35 deletions drivers/net/ethernet/qlogic/qed/qed_dev.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1149,18 +1149,10 @@ static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
return -EINVAL;
}

switch (p_hwfn->cdev->mf_mode) {
case QED_MF_DEFAULT:
case QED_MF_NPAR:
hw_mode |= 1 << MODE_MF_SI;
break;
case QED_MF_OVLAN:
if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
hw_mode |= 1 << MODE_MF_SD;
break;
default:
DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
else
hw_mode |= 1 << MODE_MF_SI;
}

hw_mode |= 1 << MODE_ASIC;

Expand Down Expand Up @@ -1507,6 +1499,11 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
p_hwfn->hw_info.ovlan);

DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
"Configuring LLH_FUNC_FILTER_HDR_SEL\n");
STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1);
}

/* Enable classification by MAC if needed */
Expand Down Expand Up @@ -1557,7 +1554,6 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,

/* send function start command */
rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
p_hwfn->cdev->mf_mode,
allow_npar_tx_switch);
if (rc) {
DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
Expand Down Expand Up @@ -1644,6 +1640,7 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
bool b_default_mtu = true;
struct qed_hwfn *p_hwfn;
int rc = 0, mfw_rc, i;
u16 ether_type;

if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
Expand Down Expand Up @@ -1677,6 +1674,24 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
if (rc)
return rc;

if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
&cdev->mf_bits) ||
test_bit(QED_MF_8021AD_TAGGING,
&cdev->mf_bits))) {
if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
ether_type = ETH_P_8021Q;
else
ether_type = ETH_P_8021AD;
STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
ether_type);
STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
ether_type);
STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
ether_type);
STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
ether_type);
}

qed_fill_load_req_params(&load_req_params,
p_params->p_drv_load_params);
rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
Expand Down Expand Up @@ -2639,31 +2654,57 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
link->pause.autoneg,
p_caps->default_eee, p_caps->eee_lpi_timer);

/* Read Multi-function information from shmem */
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
offsetof(struct nvm_cfg1, glob) +
offsetof(struct nvm_cfg1_glob, generic_cont0);
if (IS_LEAD_HWFN(p_hwfn)) {
struct qed_dev *cdev = p_hwfn->cdev;

generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
/* Read Multi-function information from shmem */
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
offsetof(struct nvm_cfg1, glob) +
offsetof(struct nvm_cfg1_glob, generic_cont0);

mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
NVM_CFG1_GLOB_MF_MODE_OFFSET;
generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);

switch (mf_mode) {
case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
break;
case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
p_hwfn->cdev->mf_mode = QED_MF_NPAR;
break;
case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
break;
mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
NVM_CFG1_GLOB_MF_MODE_OFFSET;

switch (mf_mode) {
case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
break;
case NVM_CFG1_GLOB_MF_MODE_UFP:
cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
BIT(QED_MF_LLH_PROTO_CLSS) |
BIT(QED_MF_UFP_SPECIFIC) |
BIT(QED_MF_8021Q_TAGGING);
break;
case NVM_CFG1_GLOB_MF_MODE_BD:
cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
BIT(QED_MF_LLH_PROTO_CLSS) |
BIT(QED_MF_8021AD_TAGGING);
break;
case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
BIT(QED_MF_LLH_PROTO_CLSS) |
BIT(QED_MF_LL2_NON_UNICAST) |
BIT(QED_MF_INTER_PF_SWITCH);
break;
case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
BIT(QED_MF_LLH_PROTO_CLSS) |
BIT(QED_MF_LL2_NON_UNICAST);
if (QED_IS_BB(p_hwfn->cdev))
cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
break;
}

DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
cdev->mf_bits);
}
DP_INFO(p_hwfn, "Multi function mode is %08x\n",
p_hwfn->cdev->mf_mode);

/* Read Multi-function information from shmem */
DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
p_hwfn->cdev->mf_bits);

/* Read device capabilities information from shmem */
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
offsetof(struct nvm_cfg1, glob) +
offsetof(struct nvm_cfg1_glob, device_capabilities);
Expand Down Expand Up @@ -2856,6 +2897,8 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
qed_mcp_cmd_port_init(p_hwfn, p_ptt);

qed_get_eee_caps(p_hwfn, p_ptt);

qed_mcp_read_ufp_config(p_hwfn, p_ptt);
}

if (qed_mcp_is_init(p_hwfn)) {
Expand Down Expand Up @@ -3462,7 +3505,7 @@ int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
u32 high = 0, low = 0, en;
int i;

if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
return 0;

qed_llh_mac_to_filter(&high, &low, p_filter);
Expand Down Expand Up @@ -3507,7 +3550,7 @@ void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
u32 high = 0, low = 0;
int i;

if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
return;

qed_llh_mac_to_filter(&high, &low, p_filter);
Expand Down Expand Up @@ -3549,7 +3592,7 @@ qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
u32 high = 0, low = 0, en;
int i;

if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
return 0;

switch (type) {
Expand Down Expand Up @@ -3647,7 +3690,7 @@ qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
u32 high = 0, low = 0;
int i;

if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
return;

switch (type) {
Expand Down
3 changes: 3 additions & 0 deletions drivers/net/ethernet/qlogic/qed/qed_fcoe.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -313,6 +313,9 @@ qed_sp_fcoe_conn_offload(struct qed_hwfn *p_hwfn,
p_data->d_id.addr_mid = p_conn->d_id.addr_mid;
p_data->d_id.addr_lo = p_conn->d_id.addr_lo;
p_data->flags = p_conn->flags;
if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
SET_FIELD(p_data->flags,
FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN, 1);
p_data->def_q_idx = p_conn->def_q_idx;

return qed_spq_post(p_hwfn, p_ent, NULL);
Expand Down
28 changes: 28 additions & 0 deletions drivers/net/ethernet/qlogic/qed/qed_hsi.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11993,6 +11993,16 @@ struct public_port {
#define EEE_REMOTE_TW_TX_OFFSET 0
#define EEE_REMOTE_TW_RX_MASK 0xffff0000
#define EEE_REMOTE_TW_RX_OFFSET 16

u32 oem_cfg_port;
#define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
#define OEM_CFG_CHANNEL_TYPE_OFFSET 0
#define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
#define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
#define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
#define OEM_CFG_SCHED_TYPE_OFFSET 2
#define OEM_CFG_SCHED_TYPE_ETS 0x1
#define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
};

struct public_func {
Expand Down Expand Up @@ -12069,6 +12079,23 @@ struct public_func {
#define DRV_ID_DRV_INIT_HW_MASK 0x80000000
#define DRV_ID_DRV_INIT_HW_SHIFT 31
#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)

u32 oem_cfg_func;
#define OEM_CFG_FUNC_TC_MASK 0x0000000F
#define OEM_CFG_FUNC_TC_OFFSET 0
#define OEM_CFG_FUNC_TC_0 0x0
#define OEM_CFG_FUNC_TC_1 0x1
#define OEM_CFG_FUNC_TC_2 0x2
#define OEM_CFG_FUNC_TC_3 0x3
#define OEM_CFG_FUNC_TC_4 0x4
#define OEM_CFG_FUNC_TC_5 0x5
#define OEM_CFG_FUNC_TC_6 0x6
#define OEM_CFG_FUNC_TC_7 0x7

#define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
#define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4
#define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
#define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
};

struct mcp_mac {
Expand Down Expand Up @@ -12495,6 +12522,7 @@ enum MFW_DRV_MSG_TYPE {
MFW_DRV_MSG_BW_UPDATE10,
MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
MFW_DRV_MSG_BW_UPDATE11,
MFW_DRV_MSG_OEM_CFG_UPDATE,
MFW_DRV_MSG_MAX
};

Expand Down
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