Bmb invalidation refractoring

c-thaler · May 29, 2020 · 0ea998b · 0ea998b
1 parent c993e1a
commit 0ea998b
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Showing 3 changed files with 16 additions and 12 deletions.
diff --git a/lib/src/main/scala/spinal/lib/bus/bmb/Bmb.scala b/lib/src/main/scala/spinal/lib/bus/bmb/Bmb.scala
@@ -62,6 +62,8 @@ object Bmb{
     result := (highCat @@ (base + value)).resized
     result
   }
+
+  def apply(access : BmbAccessParameter, invalidation: BmbInvalidationParameter) : Bmb = Bmb(BmbParameter(access,invalidation))
 }
 
 case class BmbMasterParameterIdMapping(range : AddressMapping, maximumPendingTransactionPerId : Int)
@@ -128,7 +130,7 @@ case class BmbParameter(addressWidth : Int,
   def wordRangeLength = log2Up(byteCount)
   def transferBeatCount = (1 << lengthWidth) / byteCount + (if(alignment.allowByte) 1 else 0)
 
-  def toAccessRequirements = BmbAccessParameter(
+  def toAccessParameter = BmbAccessParameter(
     addressWidth = addressWidth,
     dataWidth = dataWidth,
     lengthWidth = lengthWidth,
@@ -151,7 +153,9 @@ case class BmbAccessParameter(addressWidth : Int,
                               alignmentMin : Int = 0,
                               canRead : Boolean = true,
                               canWrite : Boolean = true,
-                              canExclusive : Boolean = false)
+                              canExclusive : Boolean = false){
+  def toBmbParameter() = BmbParameter(this, BmbInvalidationParameter())
+}
 
 case class BmbInvalidationParameter(canInvalidate : Boolean = false,
                                     canSync : Boolean = false,

diff --git a/lib/src/main/scala/spinal/lib/generator/BmbInterconnectGenerator.scala b/lib/src/main/scala/spinal/lib/generator/BmbInterconnectGenerator.scala
@@ -321,9 +321,9 @@ case class BmbSmpInterconnectGenerator() extends Generator{
     }
 
     val invalidationRequirementsGen2 = add task new Generator{
-      dependencies ++= connections.map(_.arbiterInvalidationRequirements)
+      dependencies ++= connections.map(_.decoderInvalidationRequirements)
       val gen = add task new Area{
-        val sInvalidationRequirements = connections.map(_.arbiterInvalidationRequirements)
+        val sInvalidationRequirements = connections.map(_.decoderInvalidationRequirements)
         var invalidationAlignement : BmbParameter.BurstAlignement.Kind = BmbParameter.BurstAlignement.LENGTH
         if(sInvalidationRequirements.exists(_.invalidateAlignment.allowWord)) invalidationAlignement = BmbParameter.BurstAlignement.WORD
         if(sInvalidationRequirements.exists(_.invalidateAlignment.allowByte)) invalidationAlignement = BmbParameter.BurstAlignement.BYTE
@@ -462,7 +462,7 @@ case class BmbSmpInterconnectGenerator() extends Generator{
         override def accessParameter(mSide: BmbAccessParameter): BmbAccessParameter = BmbUpSizerBridge.outputParameterFrom(
           inputParameter = BmbParameter(mSide, dummySlaveParameter),
           outputDataWidth = s.accessCapabilities.dataWidth
-        ).toAccessRequirements
+        ).toAccessParameter
 
         override def logic(mSide: Bmb): Bmb = {
           val c = BmbUpSizerBridge(
@@ -479,7 +479,7 @@ case class BmbSmpInterconnectGenerator() extends Generator{
         override def accessParameter(mSide: BmbAccessParameter): BmbAccessParameter = BmbDownSizerBridge.outputParameterFrom(
           inputParameter = BmbParameter(mSide, dummySlaveParameter),
           outputDataWidth = s.accessCapabilities.dataWidth
-        ).toAccessRequirements
+        ).toAccessParameter
 
         override def logic(mSide: Bmb): Bmb = {
           val c = BmbDownSizerBridge(
@@ -497,7 +497,7 @@ case class BmbSmpInterconnectGenerator() extends Generator{
           accessBridges += new Bridge {
             override def accessParameter(mSide: BmbAccessParameter): BmbAccessParameter = BmbUnburstify.outputParameter(
               inputParameter = BmbParameter(mSide, dummySlaveParameter)
-            ).toAccessRequirements
+            ).toAccessParameter
 
             override def logic(mSide: Bmb): Bmb = {
               val c = BmbUnburstify(
@@ -584,10 +584,10 @@ case class BmbSmpInterconnectGenerator() extends Generator{
 //    bus
 //  )
 
-  def addSlave(accessSource : Handle[BmbAccessParameter],
+  def addSlave(accessSource : Handle[BmbAccessParameter] = Handle[BmbAccessParameter],
                accessCapabilities : Handle[BmbAccessParameter],
                accessRequirements : Handle[BmbAccessParameter],
-               invalidationRequirements : Handle[BmbInvalidationParameter],
+               invalidationRequirements : Handle[BmbInvalidationParameter] = BmbInvalidationParameter(),
                bus : Handle[Bmb],
                mapping : Handle[AddressMapping]): Unit ={
     val model = getSlave(bus)
@@ -614,7 +614,7 @@ case class BmbSmpInterconnectGenerator() extends Generator{
   }
 
   def addConnection(m : Handle[Bmb], s : Handle[Bmb]) : this.type = {
-    val c = ConnectionModel(getMaster(m), getSlave(s), getSlave(s).mapping) //TODO .setCompositeName(m, "connector", true)
+    val c = ConnectionModel(getMaster(m), getSlave(s), getSlave(s).mapping).setCompositeName(m, "connector", true)
     getMaster(m).connections += c
     getSlave(s).connections += c
     this

diff --git a/...r/src/test/scala/spinal/tester/scalatest/SpinalSimBmbSmpInterconnectGeneratorTester.scala b/...r/src/test/scala/spinal/tester/scalatest/SpinalSimBmbSmpInterconnectGeneratorTester.scala
@@ -21,7 +21,7 @@ object SpinalSimBmbSmpInterconnectGeneratorTester {
 
       def addMaster(requirements: BmbParameter) = new Generator {
         val busHandle = Handle[Bmb]
-        interconnect.addMaster(requirements.toAccessRequirements, bus = busHandle)
+        interconnect.addMaster(requirements.toAccessParameter, bus = busHandle)
 
         val logic = add task new Area {
           val bus = slave(Bmb(requirements))
@@ -33,7 +33,7 @@ object SpinalSimBmbSmpInterconnectGeneratorTester {
         val requirements = Handle[BmbAccessParameter]
         val busHandle = Handle[Bmb]
         interconnect.addSlaveAt(
-          accessCapabilities = capabilities.toAccessRequirements,
+          accessCapabilities = capabilities.toAccessParameter,
           accessRequirements = requirements,
           bus = busHandle,
           address = address