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Fix CoreSimTest
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Dolu1990 committed Feb 11, 2020
1 parent b8520dc commit 309a0d0
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1 change: 1 addition & 0 deletions core/src/test/scala/landa/CoreSimTest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ object CoreSimTest {
dut.io.b #= b
dut.io.c #= c
cd.waitActiveEdge()
sleep(0)
if(cd.isResetDeasserted) assert(dut.io.result.toInt == ((a+b -c) & 0xFF))
}
}
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