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A Fast, Low-Overhead On-chip Network
Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
A Python package for generating HDL wrappers and top modules for HDL sources
Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.
Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
A collection of more than 170+ tools, scripts, cheatsheets and other loots that I've developed over years for Red Teaming/Pentesting/IT Security audits purposes.
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
Haptic input knob with software-defined endstops and virtual detents
Latex code for making neural networks diagrams
100 Gbps TCP/IP stack for Vitis shells
Fletcher: A framework to integrate FPGA accelerators with Apache Arrow
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
The Task Parallel System Composer (TaPaSCo)