Added generic circuits and simplified the integration of FPGA boards.

- Added generic circuits. Now it is possible to parameterize a sub circuit.
  Allows e.g. the creation of a barrel-shifter with selectable bit width.
- Circuit analyser is now able to analyse the built-in counters.
- Simplified the integration of FPGA boards.
  Board integration is now possible without creating Java code or
  even recompiling. See the BASYS3.config in examples/hdl as an example.
- Improved the label creation in the model analyzer.
- Improved performance of the boolean equation minimizer.
- Hex reader/writer supports RLE encoding like Logisim does.
- Added Spanish translation. Special thanks to Ángel Millán who provided
  the translation.
- Added a simple interactive beginners tutorial.
- Added a statistics dialog which shows the number of used components.
- Added scrollbars.
- Multiple break components are allowed.
- The fsm dialog loads the correct fsm if a circuit is open which
  is based on that fsm.
- If a VHDL defined component is used, ghdl now uses VHDL-2008.
- Added "Warren’s Crazy Small CPU" designed by Warren Toomey as a
  74xx circuit example.
- Fixed an issue in the "RAM, Chip select" component which was not fully
  asynchronous.
- Fixed swapped IC numbers 7447 and 7448.

Many small improvements.

- Improved the RAM/ROM data loader. Now binary files and Intel HEX files
  are supported.
- Added a RAM that can be synthesized on an FPGA using block RAM.
- Now its possible to create circuits using lookup tables.
- More consistent handling of the initial state in the FSM editor.
- Added a rectangle to visually group elements.
- Added a MIDI component.
- The line number and the context from the test case description is shown
  in test result table.
- Added Portuguese translation. Special thanks to Theldo Cruz Franqueira
  who provided the translation.
- Breaking changes:
  - The timing of the EEPROM with a single data port has changed.
    See help text for details.
  - The timing of the RAM with Chip Select has changed.
    See help text for details.

Added an FSM editor and SVG import

- Added a simple SVG importer to define custom shapes.
- Added an FSM editor, which allows to input a FSM, creating a associated
  truth table and finally allows to create a circuit which implements the FSM.
- Added a divider component.
- Added signed multiplications.
- Wider shapes were added, to better match the IEEE shapes to the standard.
- Added a RGB-LED.
- Added IC 74189 and IC 74382 to the Library.
- Small improvements at the test case parser.

Added a new more flexible shape for embedded circuits.

- Improved zooming and navigating in the measurement graph.
- Added multi pole double-throw relays.
- Added EEPROM with separate ports for reading and writing.
- Added a hi-color mode (5 bits per color channel) to the graphic RAM.
- The external assembly IDE is able to preload also RAMs with executable code.
  The register representing the program counter must be marked as such.
- Allows the pre-loading of program memory if a RAM is used as such, via the
  circuit settings.
- Added a new more flexible shape for embedded circuits.
- Breaking changes:
  - If you have build a processor and are using the simulators tcp interface,
    you have to flag the register which represents the program counter as such.
  - If you have used the 74xx library components with the schematic shape, you
    have to reselect the shape.
  - In your own DIL circuits you have to reselect the DIL shape in the
    circuit settings. If you have build a custom shape, you also have to
    reselect it.

Added export to Verilog

- Added a tabbed pane to the attributes dialog to make it more beginner friendly.
- Added support for asynchronous sequential circuits such as the Muller-pipeline.
  Take a look at the new asynchronous examples for illustration.
- Added export to Verilog. Special thanks to Ivan de Jesus Deras Tabora, who has
  implemented the Verilog code generator and all the necessary Verilog templates!
- All examples are translated to english.
- A "test all" function has been added to start all tests in all circuits in
  the current folder.
- Very basic support for custom shapes added.
  You must manually edit the *.dig file to add a custom shape to a circuit, so
  this is only an option for advanced users.
- It is possible to use the 74xx chips with a more schematic shape, making it
  easier to build a circuit.
- Breaking changes:
  - Added an enable input to the terminal component.
  - Added a clock input to the keyboard component.
  - In your own DIL chips, you must correct the width attribute.
    The new value can be calculated as follows: new = (old*2)-1
- Bug fixes
  - Fixed a bug in the VHDL export concerning an invalid optimization of a
    std_logic_vector access.

Significant improvement of the generated vhdl code.

- Significant improvement in the quality of the generated vhdl code.
- Its possible to define the behaviour of a component using vhdl.
  The vhdl simulator ghdl needs to be installed to use a vhdl defined component.
- Removed the high-z restrictions from the splitter.
  Now a bus can have different high z states for the different lines on the bus.
- Added new text formatting engine which supports overline, super- and subscript.
  Try "~Q_{n+1}^1" as an output label.
- When a circuit containing a ROM/EEPROM is embedded multiple times, it is now
  possible to define different ROM/EEPROM contents in each embedded instance.
- It's possible to test circuits with a high-z input which can act as an output.
- An embedded circuit that is used in the library and whose name ends with
  '-inc.dig' is shown neither in the component menu nor in the tree view.
- Added a improved counter with preset.
- Added a monoflop. Needs a clock in the circuit in order to work.
- Added a 16 segment display.
- Added a polarity aware LED.
- Added a DIP switch.
- Added a simple bidirectional splitter.
- Added ICs 74181, 74779, 7440 and 7428

improved support of 64-bit logic

- Added 64 bit support for Add and Sub components.
- Added support of some more ATF150x chips.
- Added a register file component.
- Added IC 74273
- Added an "export to zip" function.
- If an input or output has several bits, all pin numbers can be specified by a comma-separated list.
- Now it's possible to choose the polarity of the reset component.
- The model analyzer now creates an error message if a cycle is detected in the circuit.
  This prevents the generation of incorrect truth tables if, for example, a self-built
  flip-flop is analyzed.
- Added a chapter "First Steps" to the documentation.
- Bug fixes
  - Splitter, BarrelShifter and Comparator now are working with 64 bit.
  - fixed a bug in library IC 74198
- Added automated GUI tests. The overall test coverage is now above 70%.

Many small changes and improvements.

- RAM components and EEPROM now allow an input invert configuration.
- Measurement values dialog is also able to modify the values. This allows to modify
  the content of registers and flip-flops in a running simulation.
- Now you can open the measurement value table and graph in a running simulation.
- Added a bit extender component to extend signed values.
- Added a simple unclocked RS flip-flop.
- Added a bit selector component.
- Added a dual ported RAM component.
- Added a priority encoder component.
- Added tooltips showing the actual value of wires.
- Added a shortcut S to split a single wire into two wires.
- Added selectable number format to inputs and outputs.
- Now you can click in the k-map to modify the truth table.
- Improved performance through more efficient decoupling of the GUI thread and the simulation thread.
- Bug fixes
  - Fixed a bug in the RAMSinglePortSel component: Write was not edge-triggered on WE. Now it is.
  - Fixed a bug in the barrel shifter and adder if 32 bits or more where used.
  - It was not possible to use constants with 32 bits or more. Now it is.
  - Fixed a bug that caused the exported VHDL code not to work if a signal was connected
    to multiple outputs.
  - Fixed "concurrent modification exception" if input value dialog is opened.
- Breaking changes:
  - Counter modified from a asynchronous clear to a synchronous clear.

Support of custom, java implemented components

- Added the possibility to use custom, java implemented components in Digital.
- Added an EEPROM which behaves like a memory that can be written and whose content
  is non-volatile.
- Added the possibility to map keyboard keys to model buttons.
- Some small usability improvements:
  - Added a grid to the main panel.
  - Replaced shortcut 'B' with a more general attribute editing dialog (select multiple
    components and click right).
  - Added some new shortcuts (CTRL-N, CTRL-O, CTRL-A, CTRL-D).
  - Added a spinner to the input value edit dialog.
- Bug fixes
  - fixed bugs in some 74xx circuits (74160, 74161, 74162 and 74238)
  - fixed a bug in the remote interface "run to break" method.
  - fixed an error in VHDL export if comparator is used in "signed mode"
  - fixed a Windows specific bug in the speed test GUI
  - fixed a bug which causes a freezing when a file is stored in folder which contains
    a large number of sub folders and files.
- Breaking changes:
  - Removed the address bits settings from the graphic RAM. The width is now
    determined by the width and the height of the screen.

Added KV maps and VHDL export

- Added visualization of KV maps (thanks to roy77)
- Added VHDL export
  (Not yet complete, but the example processor is running on a FPGA.)
- Type of pin numbers changed from int to string to allow FPGA pin names like "U16".
- Added support for BASYS3-Board (*.xdc constrains file is written and the mixed mode
  clock manager (MMCM) is used if clock frequency exceeds 37kHz)
- Added shortcut 'B' which sets the number of data bits in all selected components.
- Breaking changes:
  - To generalize the VHDL export, an XML entity in the *.dig files had to be renamed.
    As a consequence of that the address bits settings in RAMs and ROMs
    are lost. To fix that, reset the number of address bits.
  - Added an enable input to the counter component. If you had used the counter in the
    past you have to set the en input to 1. The function of the overflow output also
    has changed (see tooltip) and now allows the cascading of counters.
  - XOR now can have more than two inputs. If you had used the XOR gate with inverted
    inputs, you have to reselect the inputs to invert.
- Some minor bug fixes.