Chisel Template

This is template project to demonstrate Chisel functionality with build scripts and tooling. The build is handled by Scala mill with some make targets for ease-of-use.

The project includes a simple module (to be replaced with your design) and also have a test spec written with the scalatest and chiseltest frameworks. The repository also have a GitHub Action to run automated tests on main branch and PRs.

Chisel Learning Resources:

• Chisel Book
• Chisel Documentation
• Chisel API

Software requirements:

• Java JDK (https://adoptium.net/installation/) - Mandatory
• Gnu Make to run the generation targets
• Verilator (as an option for simulation) - Optional
• GTKWave (to visualize VCD files) - Optional

Generating Verilog

Verilog code can be generated from Chisel by using the chisel Makefile target.

make chisel

The output verilog files are generated in the ./generated directory.

Running tests can be done with:

make test

More targets can be listed by running make.