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add parameters for instruction cache
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simont committed Oct 24, 2002
1 parent a1b4748 commit d4d7ab7
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4 changes: 4 additions & 0 deletions rtl/verilog/oc8051_defines.v
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Expand Up @@ -45,6 +45,10 @@
// ver: 1
//

//
// oc8051 cache
//
`define OC8051_CACHE

//
// operation codes for alu
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194 changes: 110 additions & 84 deletions rtl/verilog/oc8051_icache.v
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Original file line number Diff line number Diff line change
@@ -1,49 +1,52 @@
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 instruction cache ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// 8051 instruction cache ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 instruction cache ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// 8051 instruction cache ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/10/23 16:55:36 simont
// fix bugs in instruction interface
//
//

// synopsys translate_off
Expand Down Expand Up @@ -84,53 +87,73 @@ input ack_i;
input [31:0] dat_i;
output stb_o, cyc_o;
output [15:0] adr_o;
reg [15:0] adr_o;
//reg [15:0] adr_o;
reg stb_o, cyc_o;

parameter ADR_WIDTH = 6; // cache address wihth
parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)
parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)

//
// internal buffers adn wires
//
// con_buf control buffer
// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
// viald[x]=1 if block x is vaild;
reg [BL_NUM:0] vaild;
// con0, con2 contain temporal control information of current address and corrent address+2
reg [7:0] con_buf [15:0];
reg [15:0] vaild;
reg [8:0] con0, con2;
reg [7:0] cadr0, cadr2;
// part of con_buf memory
reg [14-ADR_WIDTH:0] con0, con2;
//current upper address,
reg [13-ADR_WIDTH:0] cadr0, cadr2;
reg stb_b;
// byte_select in 32 bit line (adr_i[1:0])
reg [1:0] byte_sel;
reg [1:0] cyc;
// read cycle
reg [LINE_WIDTH-1:0] cyc;
// data input from cache ram
reg [31:0] data1_i;
// temporaly data from ram
reg [15:0] tmp_data1;
reg wr1, wr1_t, stb_it;

wire [31:0] data0, data1_o;
wire cy, cy1;
wire [3:0] adr_i2;
wire [BL_WIDTH-1:0] adr_i2;
wire hit, hit_l, hit_h;
wire [5:0] adr_r, addr1;
reg [5:0] adr_w;
wire [ADR_WIDTH-1:0] adr_r, addr1;
reg [ADR_WIDTH-1:0] adr_w;
reg [15:0] mis_adr;
wire [15:0] data1;
wire [1:0] adr_r1;
wire [LINE_WIDTH-1:0] adr_r1;


assign cy = &adr_i[3:1];
assign {cy1, adr_i2} = {1'b0, adr_i[7:4]}+{4'b0000, cy};
assign cy = &adr_i[LINE_WIDTH+1:1];
assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
assign hit_l =(con0=={cadr0,1'b1});
assign hit_h =(con2=={cadr2,1'b1});
assign hit = hit_l && hit_h;

assign adr_r = adr_i[7:2] + {5'b00000, adr_i[1]};
assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
assign addr1 = wr1 ? adr_w : adr_r;
assign adr_r1 = adr_r[1:0] + 2'b01;
assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
//assign ack_o = hit;
assign ack_o = hit && stb_it;

assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];

oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[7:2]),
.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};


oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),
.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
.wr1(wr1));

defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;

always @(stb_b or data0 or data1 or byte_sel)
begin
if (stb_b) begin
Expand All @@ -140,7 +163,7 @@ begin
2'b10: dat_o = {data0[15:0], data1};
default: dat_o = {data0[7:0], data1, 8'h00};
endcase
end else begin
end else begin
dat_o = 32'h0;
end
end
Expand All @@ -151,7 +174,7 @@ begin
con0 <= #1 9'h0;
con2 <= #1 9'h0;
end else begin
con0 <= #1 {con_buf[adr_i[7:4]], vaild[adr_i[7:4]]};
con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], vaild[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
con2 <= #1 {con_buf[adr_i2], vaild[adr_i2]};
end
end
Expand All @@ -162,16 +185,16 @@ begin
cadr0 <= #1 8'h00;
cadr2 <= #1 8'h00;
end else begin
cadr0 <= #1 adr_i[15:8];
cadr2 <= #1 adr_i[15:8]+{7'h0, cy1};
cadr0 <= #1 adr_i[15:ADR_WIDTH+2];
cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;
end
end

always @(posedge clk or posedge rst)
begin
if (rst) begin
stb_b <= #1 1'b0;
byte_sel <= #1 1'b0;
byte_sel <= #1 2'b00;
end else begin
stb_b <= #1 stb_i;
byte_sel <= #1 adr_i[1:0];
Expand All @@ -182,80 +205,83 @@ always @(posedge clk or posedge rst)
begin
if (rst) begin
cyc <= #1 2'b00;
adr_o <= #1 16'd0;
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
data1_i<= #1 32'd0;
wr1 <= #1 1'b0;
adr_w <= #1 6'd0;
vaild <= #1 16'd0;
end if (stb_b && !hit && !stb_o && !wr1) begin
cyc <= #1 2'b00;
adr_o <= #1 {mis_adr[15:4], 4'b0000};
cyc <= #1 'd0;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
data1_i<= #1 32'h0;
wr1 <= #1 1'b0;
end if (stb_o && ack_i) begin
data1_i<= #1 dat_i;
wr1 <= #1 1'b1;
adr_w <= #1 adr_o[7:2];
case (cyc)
adr_w <= #1 adr_o[ADR_WIDTH+1:2];
if (&cyc) begin
cyc <= #1 2'b00;
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
vaild[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
end else begin
cyc <= #1 cyc + 1'b1;
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end


/* case (cyc)
2'b00: begin
cyc <= #1 2'b01;
adr_o <= #1 {mis_adr[15:4], 4'b0100};
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end
2'b01: begin
cyc <= #1 2'b10;
adr_o <= #1 {mis_adr[15:4], 4'b1000};
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end
2'b10: begin
cyc <= #1 2'b11;
adr_o <= #1 {mis_adr[15:4], 4'b1100};
cyc_o <= #1 1'b1;
stb_o <= #1 1'b1;
end
default: begin
cyc <= #1 2'b00;
adr_o <= #1 {mis_adr[15:4], 4'b0000};
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
vaild[mis_adr[7:4]] <= #1 1'b1;
end
endcase
/* end else if (wr1 && (cyc==2'b00)) begin
vaild[mis_adr[7:4]] <= #1 1'b1;
wr1 <= #1 1'b0;*/
endcase*/
end else begin
adr_o <= #1 {mis_adr[15:4], cyc, 2'b00};
wr1 <= #1 1'b0;
end
end

always @(posedge clk or posedge rst)
begin
if (rst)
mis_adr <= #1 16'h0000;
mis_adr <= #1 'd0;
else if (!hit_l)
mis_adr <= #1 adr_i;
else if (!hit_h)
mis_adr <= #1 adr_i+{16'd2};
end
mis_adr <= #1 adr_i+'d2;
end

always @(posedge clk or posedge rst)
begin
if (rst)
tmp_data1 <= #1 16'd0;
tmp_data1 <= #1 'd0;
else if (!hit_h && wr1 && (cyc==adr_r1))
tmp_data1 <= #1 dat_i[31:16];
else if (!hit_l && hit_h && wr1)
tmp_data1 <= #1 data1_o[31:16];
end
end

always @(posedge clk or posedge rst)
begin
Expand All @@ -264,7 +290,7 @@ begin
stb_it <= #1 1'b0;
end else begin
wr1_t <= #1 wr1;
stb_it <= #1 stb_i;
stb_it <= #1 stb_i;
end
end

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