update to MTK U-Boot (MT7621) v1.3 2020-07-13

Changelog: 2020-07-13 Add legacy dram initialization option Signed-off-by: Shiji Yang <[email protected]>
cfwarp · Sep 10, 2022 · 99c07c0 · 99c07c0
1 parent 9043b15
commit 99c07c0
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Showing 37 changed files with 568 additions and 205 deletions.
diff --git a/MTK MT7621 U-Boot User Manual.pdf b/MTK MT7621 U-Boot User Manual.pdf
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
@@ -125,6 +125,11 @@ config MACH_MT7621
 	select SUPPORT_SPL
 	select SUPPORT_TPL
 	select BINMAN
+	select SPL
+	select SPL_FRAMEWORK
+	select SPL_LEGACY_IMAGE_SUPPORT
+	select SPL_LIBCOMMON_SUPPORT
+	select SPL_LIBGENERIC_SUPPORT
 
 endchoice
 

diff --git a/arch/mips/mach-mt7621/Kconfig b/arch/mips/mach-mt7621/Kconfig
@@ -23,8 +23,7 @@ config SOC_MT7621
 	  Support MediaTek MT7621 SoC.
 
 config SYS_TEXT_BASE
-	default 0xbfc00000 if !SPL
-	default 0x80200000 if SPL
+	default 0x80200000
 
 config START_S_PATH
 	string
@@ -36,12 +35,11 @@ config SPL_START_S_PATH
 
 config SPL_TEXT_BASE
 	hex
-	default 0xbfc00000 if SPI_BOOT && !TPL
-	default 0x80100000 if NAND_BOOT || TPL
+	default 0x80100000
 
 config TPL_TEXT_BASE
 	hex
-	default 0xbfc00000 if SPI_BOOT
+	default 0xbfc00000
 
 choice
 	prompt "Board select"
@@ -60,7 +58,6 @@ config SPL_ALIGN_TO
 	hex "SPL alignment size"
 	default 0x10000 if SPI_BOOT
 	default 0x20000 if NAND_BOOT
-	depends on SPL
 	help
 	  Pad the SPL part to the closest size which is aligned with
 	  this size.
@@ -70,7 +67,6 @@ config MAX_U_BOOT_SIZE
 	hex "Maximum U-Boot size"
 	default 0x30000 if SPI_BOOT
 	default 0x80000 if NAND_BOOT
-	depends on SPL
 	help
 	  Maximum U-Boot size for SPL to search for the U-Boot SPL image
 
@@ -88,6 +84,12 @@ config MT7621_SINGLE_VPE
 	depends on MACH_MT7621
 	default n
 
+config MT7621_LEGACY_DRAMC_BIN
+	bool "Use legacy DDR initialization"
+	depends on MACH_MT7621
+	default n
+
+source "arch/mips/mach-mt7621/dramc-legacy/Kconfig"
 source "arch/mips/mach-mt7621/dramc/Kconfig"
 
 

diff --git a/arch/mips/mach-mt7621/Makefile b/arch/mips/mach-mt7621/Makefile
@@ -12,6 +12,11 @@ obj-y += cps.o
 obj-y += launch.o
 obj-y += launch_ll.o
 
+ifeq ($(CONFIG_MT7621_LEGACY_DRAMC_BIN), y)
+obj-y += dramc-legacy/
+else
 obj-y += dramc/
+endif
+
 obj-$(CONFIG_SPL_BUILD) += spl/
 obj-$(CONFIG_MT7621_MEMTEST) += memtest/
diff --git a/arch/mips/mach-mt7621/clocks.c b/arch/mips/mach-mt7621/clocks.c
@@ -20,11 +20,11 @@ int get_serial_clock(void)
 	return 50000000;
 }
 
-void mt7621_get_clocks(u32 *pcpu_clk, u32 *pbus_clk, u32 *pxtal_clk)
+void mt7621_get_clocks(u32 *pcpu_clk, u32 *pbus_clk, u32 *pddr_clk, u32 *pxtal_clk)
 {
 	void __iomem *sys_base, __iomem *dramc_base;
-	u32 bs, xtal_sel, clkcfg0, cur_clk, mempll18, dividx, fb;
-	u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk;
+	u32 bs, xtal_sel, clkcfg0, cur_clk, mempll, dividx, fb;
+	u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk, ddr_clk;
 	const static u32 xtal_div_tbl[] = {0, 1, 2, 2};
 
 	sys_base = (void __iomem *) CKSEG1ADDR(MT7621_SYSCTL_BASE);
@@ -48,9 +48,9 @@ void mt7621_get_clocks(u32 *pcpu_clk, u32 *pbus_clk, u32 *pxtal_clk)
 		cpu_clk = 500 * 1000 * 1000;
 		break;
 	case 1:
-		mempll18 = readl(dramc_base + MT7621_DRAMC_MEMPLL18_REG);
-		dividx = REG_GET_VAL(RG_MEPL_PREDIV, mempll18);
-		fb = REG_GET_VAL(RG_MEPL_FBDIV, mempll18);
+		mempll = readl(dramc_base + MT7621_DRAMC_MEMPLL18_REG);
+		dividx = REG_GET_VAL(RG_MEPL_PREDIV, mempll);
+		fb = REG_GET_VAL(RG_MEPL_FBDIV, mempll);
 		xtal_div = 1 << xtal_div_tbl[dividx];
 		cpu_clk = (fb + 1) * xtal_clk / xtal_div;
 		break;
@@ -62,25 +62,33 @@ void mt7621_get_clocks(u32 *pcpu_clk, u32 *pbus_clk, u32 *pxtal_clk)
 	ffrac = REG_GET_VAL(CUR_CPU_FFRAC, cur_clk);
 	cpu_clk = cpu_clk / ffiv * ffrac;
 
+	mempll = readl(dramc_base + MT7621_DRAMC_MEMPLL6_REG);
+	dividx = REG_GET_VAL(RG_MEPL_PREDIV, mempll);
+	fb = REG_GET_VAL(RG_MEPL_FBDIV, mempll);
+	xtal_div = 1 << xtal_div_tbl[dividx];
+	ddr_clk = fb * xtal_clk / xtal_div;
+
+	bs = readl(dramc_base + MT7621_DRAMC_MEMPLL1_REG);
+	if (REG_GET_VAL(RG_MEPL_DIV2_SEL, bs) == 0)
+		ddr_clk *= 2;
+
 	if (pcpu_clk)
 		*pcpu_clk = cpu_clk;
 
 	if (pbus_clk)
 		*pbus_clk = cpu_clk / 4;
 
+	if (pddr_clk)
+		*pddr_clk = ddr_clk;
+
 	if (pxtal_clk)
 		*pxtal_clk = xtal_clk;
 }
 
 int get_clocks(void)
 {
-	u32 xtal_clk;
-
-	mt7621_get_clocks((u32 *)&gd->cpu_clk, (u32 *)&gd->bus_clk, &xtal_clk);
-
-	gd->mem_clk = mempll_get_clock();
-
-	gd->arch.xtal_clk = xtal_clk;
+	mt7621_get_clocks((u32 *)&gd->cpu_clk, (u32 *)&gd->bus_clk,
+			  (u32 *)&gd->mem_clk, (u32 *)&gd->arch.xtal_clk);
 
 	return 0;
 }

diff --git a/arch/mips/mach-mt7621/clocks.h b/arch/mips/mach-mt7621/clocks.h
@@ -8,8 +8,7 @@
 #ifndef _MACH_MT7621_CLOCKS_H_
 #define _MACH_MT7621_CLOCKS_H_
 
-extern void mt7621_get_clocks(u32 *pcpu_clk, u32 *pbus_clk, u32 *pxtal_clk);
-extern u32 mempll_get_clock(void);
+extern void mt7621_get_clocks(u32 *pcpu_clk, u32 *pbus_clk, u32 *pddr_clk, u32 *pxtal_clk);
 extern ulong get_cpu_freq(ulong dummy);
 
 #endif /* _MACH_MT7621_CLOCKS_H_ */
diff --git a/arch/mips/mach-mt7621/cpu.c b/arch/mips/mach-mt7621/cpu.c
@@ -31,11 +31,11 @@ int print_cpuinfo(void)
 	printf("CPU:   MediaTek MT7621%cT ver %u, eco %u\n",
 	       core ? (pkg ? 'A' : 'N') : 'S', ver, eco);
 
-	mt7621_get_clocks(&cpu_clk, &bus_clk, &xtal_clk);
-	ddr_clk = mempll_get_clock();
+	mt7621_get_clocks(&cpu_clk, &bus_clk, &ddr_clk, &xtal_clk);
 
-	printf("Clocks: CPU: %dMHz, DDR: %dMHz, Bus: %dMHz, XTAL: %dMHz\n",
-		cpu_clk / 1000000, ddr_clk / 1000000, bus_clk / 1000000, xtal_clk / 1000000);
+	printf("Clocks: CPU: %dMHz, DDR: %dMHz (%dMT/s), Bus: %dMHz, XTAL: %dMHz\n",
+		cpu_clk / 1000000, ddr_clk / 1000000, ddr_clk / 500000,
+		bus_clk / 1000000, xtal_clk / 1000000);
 
 	return 0;
 }
diff --git a/arch/mips/mach-mt7621/dramc-legacy/Kconfig b/arch/mips/mach-mt7621/dramc-legacy/Kconfig
@@ -0,0 +1,70 @@
+menu "CPU & DDR configuration"
+	depends on MT7621_LEGACY_DRAMC_BIN
+
+config MT7621_CPU_FREQ_LEGACY
+	int "CPU Frequency (MHz)"
+	range 400 1200
+	default 880
+
+choice
+	prompt "DRAM Frequency"
+	default MT7621_DRAM_FREQ_1200_LEGACY
+
+config MT7621_DRAM_FREQ_400_LEGACY
+	bool "400MHz"
+
+config MT7621_DRAM_FREQ_800_LEGACY
+	bool "800MHz"
+
+config MT7621_DRAM_FREQ_1066_LEGACY
+	bool "1066MHz"
+
+config MT7621_DRAM_FREQ_1200_LEGACY
+	bool "1200MHz"
+
+endchoice
+
+choice
+	prompt "Prefered DDR2 init parameters"
+	default MT7621_DRAM_DDR2_1024M_LEGACY
+
+config MT7621_DRAM_DDR2_512M_LEGACY
+	bool "64MB"
+
+config MT7621_DRAM_DDR2_1024M_LEGACY
+	bool "128MB"
+
+config MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ_LEGACY
+	bool "W9751G6KB_A02 @ 1066MHz (64MB)"
+
+config MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ_LEGACY
+	bool "W971GG6KB25 @ 800MHz (128MB)"
+
+config MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ_LEGACY
+	bool "W971GG6KB18 @ 1066MHz (128MB)"
+
+endchoice
+
+choice
+	prompt "Prefered DDR3 init parameters"
+	default MT7621_DRAM_DDR3_2048M_LEGACY
+
+config MT7621_DRAM_DDR3_1024M_LEGACY
+	bool "128MB"
+
+config MT7621_DRAM_DDR3_1024M_KGD_LEGACY
+	bool "128MB KGD"
+
+config MT7621_DRAM_DDR3_2048M_LEGACY
+	bool "256MB"
+
+config MT7621_DRAM_DDR3_4096M_LEGACY
+	bool "512MB"
+
+endchoice
+
+config MT7621_DRAMC_DEBUG_LEGACY
+	bool "Enable verbose output during DRAMC initialization"
+	default y
+
+endmenu
diff --git a/arch/mips/mach-mt7621/dramc-legacy/Makefile b/arch/mips/mach-mt7621/dramc-legacy/Makefile
@@ -0,0 +1,21 @@
+
+obj-y += dramc.o
+
+ifeq ($(CONFIG_MT7621_DRAMC_DEBUG_LEGACY),y)
+DRAMC_BIN_FILE := mt7621_stage_sram.bin
+else
+DRAMC_BIN_FILE := mt7621_stage_sram_noprint.bin
+endif
+
+AFLAGS_dramc.o += \
+	-DDRAMC_BIN_FILE="\"$(obj)/$(DRAMC_BIN_FILE)\""
+
+spl/arch/mips/mach-mt7621/dramc-legacy/dramc.o: spl/arch/mips/mach-mt7621/dramc-legacy/$(DRAMC_BIN_FILE)
+
+spl/arch/mips/mach-mt7621/dramc-legacy/$(DRAMC_BIN_FILE): arch/mips/mach-mt7621/dramc-legacy/$(DRAMC_BIN_FILE)
+	@cp $< $@
+
+tpl/arch/mips/mach-mt7621/dramc-legacy/dramc.o: tpl/arch/mips/mach-mt7621/dramc-legacy/$(DRAMC_BIN_FILE)
+
+tpl/arch/mips/mach-mt7621/dramc-legacy/$(DRAMC_BIN_FILE): arch/mips/mach-mt7621/dramc-legacy/$(DRAMC_BIN_FILE)
+	@cp $< $@