Refactoring rx to use ser2par block

mio/hdl/mrx_protocol.v

@@ -1,51 +1,48 @@
-//##########################################################################
-//#
-//# - DW is fixed per design
-//# - size of packet being fed should be programmable
-//# - data is transmitted LSB first!
-//#
-//#
-//##########################################################################
 module mrx_protocol (/*AUTOARG*/
    // Outputs
    fifo_access, fifo_packet,
    // Inputs
-   clk, nreset, datasize, io_access, io_packet
+   clk, nreset, datasize, lsbfirst, io_access, io_packet
    );
 
    //#####################################################################
    //# INTERFACE
    //#####################################################################
 
    //parameters
-   parameter  PW   = 104;              // packet width (core)
-   parameter  MIOW  = 16;               // io packet width
-   localparam CW   = $clog2(2*PW/MIOW); // transfer count width
+   parameter  PW  = 104;            // packet width (core)
+   parameter  N   = 16;             // io packet width
+   localparam CW  = $clog2(2*PW/N); // transfer count width
 
    //clock and reset
-   input              clk;               // core clock
-   input              nreset;            // async active low reset
+   input           clk;           // core clock
+   input 	   nreset;        // async active low reset
 
    //config
-   input [CW-1:0]     datasize;          // dynamic width of output data
+   input [7:0] 	   datasize;      // dynamic width of output data
+   input 	   lsbfirst;
 
    //16 bit interface
-   input 	      io_access;    // access signal from IO
-   input [2*MIOW-1:0] io_packet;    // data from IO 
-
+   input 	   io_access;     // access signal from IO
+   input [2*N-1:0] io_packet;     // data from IO 
+   
    //wide input interface
-   output 	      fifo_access;   // access for fifo
-   output [PW-1:0]    fifo_packet;   // packet for fifo
+   output 	   fifo_access;   // access for fifo
+   output [PW-1:0] fifo_packet;   // packet for fifo
+
+   //#####################################################################
+   //# BODY
+   //#####################################################################
 
    //regs
-   reg [2:0] 	      mrx_state;
-   reg [CW-1:0]       mrx_count;   
-   reg [PW-1:0]       fifo_packet;
-   reg 		      fifo_access;
+   reg [2:0] 	   mrx_state;
+   reg [CW-1:0]    mrx_count;   
+   reg 		   fifo_access;
 
    //##########################
    //# STATE MACHINE
    //##########################
+
    `define MRX_IDLE     3'b000
    `define MRX_BUSY     3'b001
 
@@ -59,7 +56,7 @@ module mrx_protocol (/*AUTOARG*/
 	 default: mrx_state[2:0] <= 'b0;	 
        endcase // case (mrx_state[2:0])
 
-   //shift data
+   //tx word counter
    always @ (posedge clk)    
      if((mrx_state[2:0]==`MRX_IDLE) | transfer_done)
        mrx_count[CW-1:0] <= datasize[CW-1:0];
@@ -75,12 +72,28 @@ module mrx_protocol (/*AUTOARG*/
      else
        fifo_access <= transfer_done;
 
-   //create a wide parallel packet
-   always @ (posedge clk)
-     if ((mrx_state[2:0]==`MRX_BUSY))
-       fifo_packet[PW-1:0] <= {fifo_packet[PW-2*MIOW-1:0],io_packet[2*MIOW-1:0]};
-
+   //##########################
+   //# SHIFT REGISTER
+   //##########################
+
+   oh_ser2par #(.PW(PW),
+		.SW(2*N))
+
+   ser2par (// Outputs
+	    .dout	(fifo_packet[PW-1:0]),
+	    // Inputs
+	    .clk	(clk),
+	    .din	(io_packet),
+	    .lsbfirst	(lsbfirst),
+	    .shift	(1'b1)
+	    );
+
+
 endmodule // mrx_protocol
+// Local Variables:
+// verilog-library-directories:("." "../../common/hdl")
+// End:
+