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321 Open 760 Closed
321 Open 760 Closed
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Issues list

Path of FixedIO's io generated invalid target
#4714 opened Feb 20, 2025 by dtzSiFive
1
Weird paths/Targets for Module Choices
#4713 opened Feb 20, 2025 by jackkoenig
Combine LTL assert-like intrinsic factories into a single trait
#4711 opened Feb 20, 2025 by fabianschuiki
@fabianschuiki
Update ScalaDoc of LTL AssertProperty and friends Documentation Only changing documentation
#4710 opened Feb 20, 2025 by fabianschuiki
@fabianschuiki
Enable Developer Certificate of Origin (DCO) for Chisel Repositories
#4705 opened Feb 18, 2025 by bensternthal
[Chiselsim] Exit simulation on $finish bug
#4700 opened Feb 16, 2025 by seldridge
1
@seldridge
Stack Overflow when connecting Probe in FlatIO
#4687 opened Feb 13, 2025 by Emin017
1
BoringUtils: tapAndRead of literal throws error
#4663 opened Feb 4, 2025 by dtzSiFive
2
value emitVerilog is not a member of circt.stage.ChiselStage
#4603 opened Jan 9, 2025 by quantrpeter
1
SingleTargetAnnotations will report java.lang.NumberFormatException when indexing a Vec chisel type
#4575 opened Dec 24, 2024 by davine47
3
Regarding the loss of active reset behavior of Reg or being overridden by RegInit.
#4567 opened Dec 18, 2024 by linmoIO
3
chisel3.util.Queue not working with SInt bug
#4536 opened Nov 27, 2024 by jiegec
1
3
Semantic Inconsistency in Intermediate FIRRTL File During Compilation: Incorrect reg Emission Instead of node and Loss of Memory readUnderWrite Behavior
#4526 opened Nov 25, 2024 by linmoIO
2
Initialize (FPGA) memory in Chisel 6
#4496 opened Nov 6, 2024 by schoeberl
1
Need for explicit widths in BlackBox parameters
#4488 opened Oct 26, 2024 by HakamAtassi
Selecting instances when using D/I and Class Property types crashes
#4476 opened Oct 16, 2024 by jackkoenig
1
Layers not emitted when used as colors of probes with separate elaboration
#4469 opened Oct 15, 2024 by dtzSiFive
PriorityMux drops arguments if input sequences are not the same size bug good first issue An issue whose fix is simple. Perfect for a new developer wanting to get involved!
#4444 opened Oct 4, 2024 by jackkoenig
1
SyncReadMem ruw (ReadUnderWrite) parameter has no effect
#4433 opened Oct 2, 2024 by maxbjurling
2
Probe color should be checked for read bug
#4406 opened Sep 19, 2024 by dtzSiFive
Lexical scope is not properly checked for ports of submodules bug
#4405 opened Sep 18, 2024 by jackkoenig
2
Update docs/README.md good first issue An issue whose fix is simple. Perfect for a new developer wanting to get involved!
#4402 opened Sep 16, 2024 by jackkoenig
1
bundleWithABoolProbe := 0.U.asTypeOf(bundleWithABoolProbe) results in illegal firrtl bug
#4388 opened Sep 10, 2024 by mwachs5
Path values do not work with multiple instantiation bug
#4379 opened Sep 3, 2024 by jackkoenig 7.0
Wrong memory initialization with ChiselSim bug
#4340 opened Aug 12, 2024 by rameloni
2
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