This repository contains all the assignments for ECE 3700. It is updated periodically.

File list (root directory):

• README.md -- Markdown version of README file
• README.html -- HTML version
• 3700.css -- CSS style for HTML documents
• Basys3_Master.xdc -- Constraint file template for Basys3 board
• workflows/ -- instructions for downloading, completing and uploading assignments.

Assignments:

Assignments in the file tree below are updated periodically. You should sync new updates by running these commands from within this directory in the terminal:

git fetch upstream
git merge upstream/master

Listing for First Four Weeks

The first assignment group is designed to teach Verilog syntax for Register Transfer Level (RTL) design. You should plan to complete approximately one assignment per weekday. Some will go faster than others; if you complete an assignment in under one hour, you should continue working on the next assignment.

• 1_verilog/ -- First assignment group for the semester. Assignments are organized into weekly subgroups:
  • 1_modules/
    • 1_simple_module/
    • 2_build/
    • 3_parameters/
    • 4_tasks/
    • 5_functions/
  • 2_operations/
    • 1_unary/
    • 2_bitwise/
    • 3_logical/
    • 4_unsigned/
    • 5_signed/
  • 3_loops_conditionals/
    • 1_for_loops/
    • 2_while_loops/
    • 3_generate/
    • 4_case/
    • 5_conditional/
• 2_rtl/ -- Second assignment group with weekly subgroups:
  • 1_state_machines/
    • 1_keypad/
    • 2_debouncer/
    • 3_handshaking/
    • 4_serial_interface/
  • 2_communication/
    • 1_SPI_READ/
    • 2_SPI_WRITE/
    • 3_UART_TX/
    • 4_UART_RX/
    • 5_UART_bidir/
  • 3_memory/
    • 1_RAM/