finished chapter 2.5

project02.5/ClkRSLatch.hdl

@@ -0,0 +1,16 @@
+CHIP ClkRSLatch {
+
+  // The conventional abbreviation for the clock input is 'clk'
+  // but there is a bug in the Hardware Simulator that confuses
+  // that signal name with the internal DFF clock.
+
+  IN  s, r, ck;
+  OUT q, q-;
+
+  PARTS:
+  SNand(a=s, b=ck, out=s-);
+  SNand(a=r, b=ck, out=r-);
+  SNand(a=s-, b=qq-, out=q, out=qq);
+  SNand(a=r-, b=qq, out=q-, out=qq-);
+}
+

project02.5/ClkRSLatch.tst

@@ -0,0 +1,63 @@
+load ClkRSLatch.hdl,
+output-file ClkRSLatch.out,
+
+// Important: the latch must be initialized set or reset 
+set s 0,
+set r 1,
+set ck 1,
+repeat 5 { tick, tock; }
+set ck 0,
+repeat 5 { tick, tock; }
+
+output-list time%S1.4.1 s%B2.1.2 r%B2.1.2 ck%B2.1.2 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Hold
+set ck 0,
+set s 0,	
+set r 0,
+repeat 4 { tick, output; tock, output; }
+
+// Ignore s
+set s 1,	
+repeat 2 { tick, output; tock, output; }
+
+// Ignore s+r
+set r 1,	
+repeat 2 { tick, output; tock, output; }
+
+// Ignore r
+set s 0,
+set r 1,	
+repeat 2 { tick, output; tock, output; }
+
+set r 0,	
+repeat 2 { tick, output; tock, output; }
+
+output-list time%S1.4.1 s%B2.1.2 r%B2.1.2 ck%B2.1.2 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Set
+set ck 1,
+repeat 2 { tick, output; tock, output; }
+set s 1,
+repeat 4 { tick, output; tock, output; }
+
+// Hold
+set s 0,
+repeat 4 { tick, output; tock, output; }
+
+output-list time%S1.4.1 s%B2.1.2 r%B2.1.2 ck%B2.1.2 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Reset
+set r 1,
+repeat 4 { tick, output; tock, output; }
+
+// Hold
+set ck 0,
+repeat 2 { tick, output; tock, output; }
+set r 0,
+repeat 2 { tick, output; tock, output; }
+set s 1,
+repeat 4 { tick, output; tock, output; }
+
+output-list time%S1.4.1 s%B2.1.2 r%B2.1.2 ck%B2.1.2 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+

project02.5/DFFn.hdl

@@ -0,0 +1,21 @@
+CHIP DFFn {
+
+  // The conventional abbreviation for the clock input is 'clk'
+  // but there is a bug in the Hardware Simulator that confuses
+  // that signal name with the internal DFF clock.
+
+    IN  d, ck;
+    OUT q, q-;
+
+    PARTS:
+    SNand(a=d, b=ck, out=s1-);
+    SNand(a=s1-, b=ck, out=r1-);
+    SNand(a=s1-, b=q1-, out=q1);
+    SNand(a=r1-, b=q1, out=q1-);
+    SNot(in=ck, out=ck-);
+    SNand(a=q1, b=ck-, out=s2-);
+    SNand(a=q1-, b=ck-, out=r2-);
+    SNand(a=s2-, b=q2-, out=q2, out=q);
+    SNand(a=r2-, b=q2, out=q2-, out=q-);
+}
+

project02.5/DFFn.tst

@@ -0,0 +1,53 @@
+load DFFn.hdl,
+output-file DFFn.out,
+
+// Important: the latch must be initialized set or reset 
+set d 0,
+set ck 1,
+repeat 5 { tick, tock; }
+set ck 0,
+repeat 5 { tick, tock; }
+
+
+output-list time%S1.4.1 d%B2.1.2 ck%B2.1.2 s1-%B2.1.2 r1-%B2.1.2
+    q1%B2.1.2 q1-%B2.1.2 ck-%B2.1.2 s2-%B2.1.2 r2-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Hold master FF -- d ignored
+set ck 0,
+set d 1,	
+repeat 4 { tick, output; tock, output; }
+
+set d 0,	
+repeat 4 { tick, output; tock, output; }
+
+
+output-list time%S1.4.1 d%B2.1.2 ck%B2.1.2 s1-%B2.1.2 r1-%B2.1.2
+    q1%B2.1.2 q1-%B2.1.2 ck-%B2.1.2 s2-%B2.1.2 r2-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Set master FF -- clk before d
+set ck 1,
+repeat 2 { tick, output; tock, output; }
+set d 1,
+repeat 4 { tick, output; tock, output; }
+
+// Transfer to slave FF
+set ck 0,
+repeat 5 { tick, output; tock, output; }
+
+
+output-list time%S1.4.1 d%B2.1.2 ck%B2.1.2 s1-%B2.1.2 r1-%B2.1.2
+    q1%B2.1.2 q1-%B2.1.2 ck-%B2.1.2 s2-%B2.1.2 r2-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Reset master FF -- d before clk
+set d 0,
+repeat 2 { tick, output; tock, output; }
+set ck 1,
+repeat 4 { tick, output; tock, output; }
+
+// Transfer to slave FF
+set ck 0,
+repeat 5 { tick, output; tock, output; }
+
+output-list time%S1.4.1 d%B2.1.2 ck%B2.1.2 s1-%B2.1.2 r1-%B2.1.2
+    q1%B2.1.2 q1-%B2.1.2 ck-%B2.1.2 s2-%B2.1.2 r2-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+

project02.5/RSFF.hdl

@@ -0,0 +1,21 @@
+CHIP RSFF {
+
+  // The conventional abbreviation for the clock input is 'clk'
+  // but there is a bug in the Hardware Simulator that confuses
+  // that signal name with the internal DFF clock.
+
+    IN  s, r, ck;
+    OUT q, q-;
+
+    PARTS:
+    SNand(a=s, b=ck, out=s1-);
+    SNand(a=r, b=ck, out=r1-);
+    SNand(a=s1-, b=q1-, out=q1);
+    SNand(a=r1-, b=q1, out=q1-);
+    SNot(in=ck, out=ck-);
+    SNand(a=q1, b=ck-, out=s2-);
+    SNand(a=q1-, b=ck-, out=r2-);
+    SNand(a=s2-, b=q2-, out=q2, out=q);
+    SNand(a=r2-, b=q2, out=q2-, out=q-);
+}
+

project02.5/RSFF.tst

@@ -0,0 +1,49 @@
+load RSFF.hdl,
+output-file RSFF.out,
+
+// Important: the latch must be initialized set or reset 
+set s 0,
+set r 1,
+set ck 1,
+repeat 5 { tick, tock; }
+set r 0,
+set ck 0,
+repeat 5 { tick, tock; }
+
+output-list time%S1.4.1 s%B2.1.2 r%B2.1.2 ck%B2.1.2 s1-%B2.1.2 r1-%B2.1.2
+    q1%B2.1.2 q1-%B2.1.2 ck-%B2.1.2 s2-%B2.1.2 r2-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Hold
+set ck 0,
+set s 0,	
+set r 0,
+
+tick, output; tock, output;
+
+// set pulse while clock high
+set ck 1,
+repeat 2 { tick, output; tock, output; }
+set s 1,
+repeat 4 { tick, output; tock, output; }
+set s 0,
+tick, output; tock, output;
+set ck 0,
+repeat 5 { tick, output; tock, output; }
+
+output-list time%S1.4.1 s%B2.1.2 r%B2.1.2 ck%B2.1.2 s1-%B2.1.2 r1-%B2.1.2
+    q1%B2.1.2 q1-%B2.1.2 ck-%B2.1.2 s2-%B2.1.2 r2-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// clock pulse while reset high
+set r 1,
+repeat 2 { tick, output; tock, output; }
+set ck 1,
+repeat 4 { tick, output; tock, output; }
+set ck 0,
+tick, output; tock, output;
+set r 0,
+repeat 5 { tick, output; tock, output; }
+
+output-list time%S1.4.1 s%B2.1.2 r%B2.1.2 ck%B2.1.2 s1-%B2.1.2 r1-%B2.1.2
+    q1%B2.1.2 q1-%B2.1.2 ck-%B2.1.2 s2-%B2.1.2 r2-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+

project02.5/RSLatch.hdl

@@ -0,0 +1,9 @@
+CHIP RSLatch {
+  IN s-, r-;
+  OUT q, q-;
+
+  PARTS:
+  SNand(a=s-, b=qq-, out=qq, out=q);
+  SNand(a=r-, b=qq, out=qq-, out=q-);
+
+}

project02.5/RSLatch.tst

@@ -0,0 +1,49 @@
+load RSLatch.hdl,
+output-file RSLatch.out,
+output-list time%S1.4.1 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Important: the latch must be initialized set or reset 
+set s- 1,
+set r- 0,
+repeat 10 { tick, tock; }
+
+// Hold
+set s- 1,	
+set r- 1,
+repeat 4 { tick, output; tock, output; }
+
+// Set
+set s- 0,
+repeat 4 { tick, output; tock, output; }
+
+output-list time%S1.4.1 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Hold
+set s- 1,
+repeat 4 { tick, output; tock, output; }
+
+// Reset
+set r- 0,
+repeat 4 { tick, output; tock, output; }
+
+output-list time%S1.4.1 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+
+// Hold
+set r- 1,
+repeat 4 { tick, output; tock, output; }
+
+// Set
+set s- 0,
+repeat 2 { tick, output; tock, output; }
+
+// Set and Reset -- illegal
+set r- 0,
+repeat 4 { tick, output; tock, output; }
+
+// Hold, but simulated circuit oscillates
+set s- 1,
+set r- 1,
+
+repeat 4 { tick, output; tock, output; }
+output-list time%S1.4.1 s-%B2.1.2 r-%B2.1.2 q%B2.1.2 q-%B2.1.2;
+

project02.5/SNand.hdl

@@ -0,0 +1,8 @@
+CHIP SNand {
+  IN a, b;
+  OUT out;
+
+  PARTS:
+  Nand(a=a, b=b, out=x);
+  DFF(in=x, out=out);
+}

project02.5/SNot.hdl

@@ -0,0 +1,11 @@
+/// SNot -- Synchronized Not gate
+
+CHIP SNot {
+
+    IN  in;
+    OUT out;
+
+    PARTS:
+    Not(in=in, out=x);
+    DFF(in=x, out=out);
+}