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Commits on Jan 30, 2023

• Rework parameter handling in testbench makefiles

  Show description for b81e323
  alexforencich

  committed
  b81e323

Commits on Nov 2, 2022

• Add option for output FIFO to improve pipelining and RAM inference for large FIFOs

  Show description for 9c3409f
  alexforencich

  committed
  9c3409f

Commits on Nov 1, 2022

• Replace OUTPUT_PIPELINE with RAM_PIPELINE

  Show description for a0f4680
  alexforencich

  committed
  a0f4680

Commits on Mar 30, 2022

• Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8

  alexforencich

  committed
  073d50d

Commits on Dec 11, 2021

• Use start_soon instead of fork

  alexforencich

  committed
  4df34f1

Commits on Nov 29, 2021

• Testbench parameter cleanup

  alexforencich

  committed
  2a89fb9

• Add support to demux for routing by tdest

  alexforencich

  committed
  907081d

• Add UPDATE_TID parameter to set MSBs of tid based on source port

  alexforencich

  committed
  ccbca0c

Commits on Nov 25, 2021

• Decouple tid/tdest signal widths for routing components

  alexforencich

  committed
  2486339

Commits on Nov 15, 2021

• Remove deprecated assigments

  alexforencich

  committed
  f40e683

Commits on Oct 13, 2021

• Split async FIFO resets

  alexforencich

  committed
  4f1eaba

Commits on Sep 28, 2021

• More tests for pipeline FIFO

  alexforencich

  committed
  e0da181

• Reorganize test lists

  alexforencich

  committed
  e48901a

• Test async FIFO with different clock periods

  alexforencich

  committed
  d549267

Commits on Aug 27, 2021

• Bypass pipeline FIFO when length is zero

  alexforencich

  committed
  6bcd96f

Commits on Aug 26, 2021

• Add axis_pipeline_fifo

  alexforencich

  committed
  6a030f5

• Add DROP_OVERSIZE_FRAME parameter

  alexforencich

  committed
  92681fa

Commits on Aug 17, 2021

• add LAST_ENABLE to axis_arb_mux

  lomotos10

  committed
  edaec3b

Commits on Jun 2, 2021

• Remove string parameters

  alexforencich

  committed
  4fa3870

Commits on May 30, 2021

• Add switch testbenches

  alexforencich

  committed
  5d9c982

• Use cocotb.top

  alexforencich

  committed
  9417d5f

Commits on May 25, 2021

• Add tuser assert tests

  alexforencich

  committed
  c1bfa8c

• Add stress tests

  alexforencich

  committed
  a7905ed

• Add arbitration test

  alexforencich

  committed
  a7ebfdc

Commits on Apr 3, 2021

• Add cocotb testbenches

  alexforencich

  committed
  74c1014

Commits on Sep 7, 2020

• Add PIPELINE_OUTPUT parameter to FIFO adapter modules

  alexforencich

  committed
  ede73b4

• Add pararametrizable output pipeline to FIFOs

  alexforencich

  committed
  2f88368

Commits on Sep 3, 2020

• Pipeline RAM output in RAM switch

  alexforencich

  committed
  a7689b6

Commits on Feb 18, 2020

• Add AXI stream RAM switch module and testbenches

  alexforencich

  committed
  52d1117

Commits on Jul 24, 2019

• Pass all parameters in testbenches

  alexforencich

  committed
  8179a32

Commits on Jul 18, 2019

• Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH

  alexforencich

  committed
  69de6fd

Commits on Jul 16, 2019

• Unconditionally wait at least one delta cycle

  alexforencich

  committed
  1d5a4db

Commits on Apr 27, 2019

• Add FIFO/width adapter wrapper modules

  alexforencich

  committed
  8e969aa

• Test shorter frames

  alexforencich

  committed
  e3fcb0f

Commits on Mar 29, 2019

• Change parameter concatenation to increments of DEST_WIDTH

  alexforencich

  committed
  a9c7946

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