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Lectures for the Agile Hardware Design course in Jupyter Notebooks
Open-source high-performance RISC-V processor
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
KLayout technology files for FreePDK45
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Raspberry Pi + High Quality Camera = High-quality USB Webcam!
Chisel wrappers and examples for Convey's Wolverine FPGA accelerators
An NTNU thesis LaTeX document class for bachelor, master, and PhD theses
A zynq host-platform shell for midas generated simulators.
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
EECS-NTNU / riscv-boom
Forked from riscv-boom/riscv-boomBOOM: Berkeley Out-of-Order Machine
EECS-NTNU / rocket-chip
Forked from chipsalliance/rocket-chipRocket Chip Generator