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  1. UVM_work UVM_work Public

    uvm projects and lab sessions

    SystemVerilog

  2. OpenSTA OpenSTA Public

    Forked from nickson-jose/OpenSTA

    OpenSTA engine

    C++

  3. System_Verilog System_Verilog Public

    SystemVerilog 1

  4. vsdflow vsdflow Public

    Forked from kunalg123/vsdflow

    VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

    Verilog

  5. vsdmixedsignalflow vsdmixedsignalflow Public

    Forked from praharshapm/vsdmixedsignalflow

    This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to …

    Verilog

  6. vsdstdcelldesign vsdstdcelldesign Public

    Forked from nickson-jose/vsdstdcelldesign

    This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an…

    Verilog