use ram

climber.vhd

@@ -2,16 +2,20 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.std_logic_unsigned.all;
 use IEEE.std_logic_arith.all;
+use IEEE.std_logic_misc.all;
 use work.types.all;
 
 entity climber is
     port (
         clk  : in  std_logic := '0';
         go   : in  std_logic := '0';
         root : in  std_logic_vector(9 downto 0) := (others => '0');
+        hit  : in  std_logic := '0';
+        data : in  data_t := ((others => '0'), (others => '0'));
         peak : out std_logic_vector(17 downto 0) := (others => '0');
         len  : out std_logic_vector(7 downto 0) := (others => '0');
-        done : out std_logic := '0'
+        done : out std_logic := '0';
+        addr : out std_logic_vector(8 downto 0) := (others => '0')
     );
 end climber;
 
@@ -21,11 +25,24 @@ architecture RTL of climber is
     signal peak_reg : std_logic_vector(17 downto 0) := (others => '0');
     signal len_reg  : std_logic_vector(7 downto 0) := (others => '0');
 
+    signal len_reg_prev : std_logic_vector(7 downto 0) := (others => '0');
+
+    signal valid : std_logic := '0';
+
 begin
 
     peak <= peak_reg;
     len  <= len_reg;
     done <= '1' when root_reg = 1 else '0';
+    addr <= root_reg(9 downto 1);
+
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            valid <= nor_reduce(root_reg(17 downto 10));
+            len_reg_prev <= len_reg;
+        end if;
+    end process;
 
     process(clk)
 
@@ -41,7 +58,17 @@ begin
                 root_var := "00000000" & root;
                 peak_var := (others => '0');
                 len_var  := (others => '0');
-            else
+            elsif (valid = '1' and hit = '1' and root_reg /= 1) then
+                root_var := "000000000000000001";
+
+                if data.peak < peak_reg then
+                    peak_var := peak_reg;
+                else
+                    peak_var := data.peak;
+                end if;
+
+                len_var := len_reg_prev + data.len;
+            elsif root_reg /= 1 then
                 root_var := root_reg;
                 peak_var := peak_reg;
                 len_var  := len_reg;

collatz.qsf

@@ -1,12 +1,12 @@
 # -------------------------------------------------------------------------- #
 #
 # Copyright (C) 2017  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Intel Program License 
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
 # Subscription Agreement, the Intel Quartus Prime License Agreement,
 # the Intel FPGA IP License Agreement, or other applicable license
 # agreement, including, without limitation, that your use is for
@@ -54,11 +54,6 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name VHDL_FILE types.vhd
-set_global_assignment -name VHDL_FILE testbench.vhd
-set_global_assignment -name VHDL_FILE sorter.vhd
-set_global_assignment -name VHDL_FILE collatz.vhd
-set_global_assignment -name VHDL_FILE climber.vhd
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench
 set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench -section_id eda_simulation
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench -section_id testbench
@@ -67,4 +62,13 @@ set_global_assignment -name EDA_TEST_BENCH_FILE testbench.vhd -section_id testbe
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name MIF_FILE ram.mif
+set_global_assignment -name VHDL_FILE ram.vhd
+set_global_assignment -name VHDL_FILE types.vhd
+set_global_assignment -name VHDL_FILE testbench.vhd
+set_global_assignment -name VHDL_FILE sorter.vhd
+set_global_assignment -name VHDL_FILE collatz.vhd
+set_global_assignment -name VHDL_FILE climber.vhd
+set_global_assignment -name QIP_FILE ram_ip.qip

collatz.vhd

@@ -19,9 +19,12 @@ architecture RTL of collatz is
             clk  : in  std_logic;
             go   : in  std_logic;
             root : in  std_logic_vector(9 downto 0);
+            hit  : in  std_logic;
+            data : in  data_t;
             peak : out std_logic_vector(17 downto 0);
             len  : out std_logic_vector(7 downto 0);
-            done : out std_logic
+            done : out std_logic;
+            addr : out std_logic_vector(8 downto 0)
         );
     end component;
 
@@ -33,8 +36,18 @@ architecture RTL of collatz is
         );
     end component;
 
-    signal clk_count_reg : std_logic_vector(31 downto 0) := (others => '0');
+    component ram is
+        port (
+            clk          : in  std_logic;
+            write_enable : in  std_logic;
+            addr         : in  std_logic_vector(8 downto 0);
+            data_in      : in  data_t;
+            hit          : out std_logic;
+            data_out     : out data_t
+        );
+    end component;
 
+    signal clk_count_reg : std_logic_vector(31 downto 0) := (others => '0');
     signal alldone : std_logic := '0';
 
     signal go   : std_logic := '1';
@@ -47,25 +60,46 @@ architecture RTL of collatz is
 
     signal chain_reg : chain_t := ((others => '0'), (others => '0'), (others => '0'));
 
+    signal write_enable  : std_logic := '0';
+    signal addr_chain    : std_logic_vector(8 downto 0) := (others => '0');
+    signal addr_ram      : std_logic_vector(8 downto 0) := (others => '0');
+    signal hit           : std_logic := '0';
+    signal data_in       : data_t := ((others => '0'), (others => '0'));
+    signal data_out      : data_t := ((others => '0'), (others => '0'));
+
 begin
 
     climber_p : climber port map(
         clk  => clk,
         go   => go,
         root => root_chain,
+        hit  => hit,
+        data => data_out,
         peak => peak,
         len  => len,
-        done => done(0)
+        done => done(0),
+        addr => addr_chain
     );
 
-    sorter_p : sorter port map(
+    sorter_p : sorter port map (
         clk   => clk,
         chain => chain_reg,
         top4  => top4
     );
 
+    ram_p : ram port map (
+        clk          => clk,
+        write_enable => write_enable,
+        addr         => addr_ram,
+        data_in      => data_in,
+        hit          => hit,
+        data_out     => data_out
+    );
+
     clk_count <= clk_count_reg;
     root_chain <= root & '1';
+    data_in <= (peak, len);
+    addr_ram <= root - 1 when write_enable = '1' else addr_chain;
 
     process(clk, alldone)
     begin
@@ -79,6 +113,7 @@ begin
         if rising_edge(clk) then
             if (done = "01" and alldone = '0') then
                 chain_reg <= (root & '1', peak, len);
+                write_enable <= '1';
                 root <= root + 1;
 
                 if root >= 511 then
@@ -87,6 +122,7 @@ begin
                     go <= '1';
                 end if;
             else
+                write_enable <= '0';
                 go <= '0';
             end if;
 

ram.mif

@@ -0,0 +1,25 @@
+-- Copyright (C) 2017  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=27;
+DEPTH=512;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	[0..511]  :   0;
+END;

ram.vhd

@@ -0,0 +1,49 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+use work.types.all;
+
+entity ram is
+    port (
+        clk          : in  std_logic := '0';
+        write_enable : in  std_logic := '0';
+        addr         : in  std_logic_vector(8 downto 0) := (others => '0');
+        data_in      : in  data_t := ((others => '0'), (others => '0'));
+        hit          : out std_logic := '0';
+        data_out     : out data_t := ((others => '0'), (others => '0'))
+    );
+end ram;
+
+architecture RTL of ram is
+
+    component ram_ip
+        port (
+            address : in  std_logic_vector(8 downto 0);
+            clock   : in  std_logic;
+            data    : in  std_logic_vector(26 downto 0);
+            wren    : in  std_logic;
+            q       : out std_logic_vector(26 downto 0)
+        );
+    end component;
+
+    signal data : std_logic_vector(26 downto 0) := (others => '0');
+    signal q    : std_logic_vector(26 downto 0) := (others => '0');
+
+begin
+
+    ram_ip_p : ram_ip port map (
+        address => addr,
+        clock   => clk,
+        data    => data,
+        wren    => write_enable,
+        q       => q
+    );
+
+    data <= write_enable & data_in.peak & data_in.len;
+
+    hit <= q(26);
+    data_out.peak <= q(25 downto 8);
+    data_out.len  <= q(7 downto 0);
+
+end RTL;

ram_ip.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram_ip.vhd"]