Bump to latest version

Merge remote-tracking branch 'upstream/master'

firmware/common/LPC4330_M4_memory.ld

@@ -20,7 +20,7 @@
  * Boston, MA 02110-1301, USA.
  */
 
-/* Linker script for HackRF Jellybean/Jawbreaker (LPC4330, 1M SPI flash, 264K SRAM). */
+/* Linker script for Rad1o badge - (LPC4330, 1M SPI flash, 264K SRAM). */
 
 MEMORY
 {

firmware/common/hackrf_core.c

@@ -470,8 +470,7 @@ bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
 	return bandwidth_hz_real != 0;
 }
 
-/* clock startup for Jellybean with Lemondrop attached
-Configure PLL1 to max speed (204MHz).
+/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
 Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */ 
 void cpu_clock_init(void)
 {
@@ -491,78 +490,43 @@ void cpu_clock_init(void)
 	si5351c_configure_pll_sources(&clock_gen);
 	si5351c_configure_pll_multisynth(&clock_gen);
 
-#if (defined JAWBREAKER || defined HACKRF_ONE)
 	/*
-	 * Jawbreaker clocks:
+	 * Clocks:
 	 *   CLK0 -> MAX5864/CPLD
 	 *   CLK1 -> CPLD
 	 *   CLK2 -> SGPIO
-	 *   CLK3 -> external clock output
-	 *   CLK4 -> RFFC5072
-	 *   CLK5 -> MAX2837
+	 *   CLK3 -> External Clock Output (power down at boot)
+	 *   CLK4 -> RFFC5072 (MAX2837 on rad1o)
+	 *   CLK5 -> MAX2837 (MAX2871 on rad1o)
 	 *   CLK6 -> none
-	 *   CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal)
+	 *   CLK7 -> LPC43xx (uses a 12MHz crystal by default)
 	 */
 
-	/* MS3/CLK3 is the source for the external clock output. */
-	si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
-
-	/* MS4/CLK4 is the source for the RFFC5071 mixer. */
-	si5351c_configure_multisynth(&clock_gen, 4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
-
- 	/* MS5/CLK5 is the source for the MAX2837 clock input. */
-	si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
-
-	/* MS6/CLK6 is unused. */
-	/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
-	uint8_t ms7data[] = { 90, 255, 20, 0 };
-	si5351c_write(&clock_gen, ms7data, sizeof(ms7data));
-#endif
-
-#ifdef RAD1O
-	/* rad1o clocks:
-	 *   CLK0 -> MAX5864/CPLD
-	 *   CLK1 -> CPLD
-	 *   CLK2 -> SGPIO
-	 *   CLK3 -> External Clock Output
-	 *   CLK4 -> MAX2837
-	 *   CLK5 -> MAX2871
-	 *   CLK6 -> none
-	 *   CLK7 -> LPC4330 (but LPC4330 starts up on its own crystal) */
-
-	/* MS3/CLK3 is the source for the external clock output. */
-	si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
-
-	/* MS4/CLK4 is the source for the MAX2837 clock input. */
+	/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
 	si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
-
-	/* MS5/CLK5 is the source for the RFFC5071 mixer. */
+ 	/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
 	si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
 
 	/* MS6/CLK6 is unused. */
+	/* MS7/CLK7 is unused. */
 
-	/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
-	uint8_t ms7data[] = { 90, 255, 20, 0 };
-	si5351c_write(&clock_gen, ms7data, sizeof(ms7data));
-#endif
-
-	/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
+	/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
 	sample_rate_set(10000000);
 
 	si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
 	// soft reset
-	uint8_t resetdata[] = { 177, 0xac };
-	si5351c_write(&clock_gen, resetdata, sizeof(resetdata));
+	// uint8_t resetdata[] = { 177, 0xac };
+	// si5351c_write(&clock_gen, resetdata, sizeof(resetdata));
+	si5351c_reset_pll(&clock_gen);
 	si5351c_enable_clock_outputs(&clock_gen);
 
 	//FIXME disable I2C
 	/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
 	i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
 
 	/*
-	 * 12MHz clock is entering LPC XTAL1/OSC input now.  On
-	 * Jellybean/Lemondrop, this is a signal from the clock generator.  On
-	 * Jawbreaker, there is a 12 MHz crystal at the LPC.
+	 * 12MHz clock is entering LPC XTAL1/OSC input now.
+	 * On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
 	 * Set up PLL1 to run from XTAL1 input.
 	 */
 
@@ -634,6 +598,7 @@ void cpu_clock_init(void)
 	CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1)
 			| CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
 
+#if (defined JAWBREAKER || defined HACKRF_ONE)
 	/* Disable unused clocks */
 	/* Start with PLLs */
 	CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1);
@@ -699,6 +664,13 @@ void cpu_clock_init(void)
 	// CCU2_CLK_APB2_USART3_CFG = 0;
 	// CCU2_CLK_APLL_CFG = 0;
 	// CCU2_CLK_SDIO_CFG = 0;
+#endif
+
+#ifdef RAD1O
+	/* Disable unused clock outputs. They generate noise. */
+	scu_pinmux(CLK0, SCU_CLK_IN | SCU_CONF_FUNCTION7);
+	scu_pinmux(CLK2, SCU_CLK_IN | SCU_CONF_FUNCTION7);
+#endif
 }
 
 

firmware/common/rffc5071.c

@@ -208,7 +208,7 @@ void rffc5071_enable(rffc5071_driver_t* const drv)  {
 }
 
 #define LO_MAX 5400
-#define REF_FREQ 50
+#define REF_FREQ 40
 #define FREQ_ONE_MHZ (1000*1000)
 
 /* configure frequency synthesizer in integer mode (lo in MHz) */

firmware/common/si5351c.c

@@ -116,11 +116,11 @@ void si5351c_configure_pll_sources(si5351c_driver_t* const drv)
 /* MultiSynth NA (PLLA) and NB (PLLB) */
 void si5351c_configure_pll_multisynth(si5351c_driver_t* const drv)
 {
-	//init plla to (0x0e00+512)/128*25mhz xtal = 800mhz -> int mode
+	/*PLLA: 25MHz XTAL * (0x0e00+512)/128 = 800mhz -> int mode */
 	uint8_t data[] = { 26, 0x00, 0x01, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00 };
 	si5351c_write(drv, data, sizeof(data));
 
-	/* 10 MHz input on CLKIN for PLLB */
+	/*PLLB: 10MHz CLKIN * (0x2600+512)/128 = 800mhz */
 	data[0] = 34;
 	data[4] = 0x26;
 	si5351c_write(drv, data, sizeof(data));
@@ -164,73 +164,49 @@ void si5351c_configure_multisynth(si5351c_driver_t* const drv,
 	si5351c_write(drv, data, sizeof(data));
 }
 
-#if (defined JAWBREAKER || defined HACKRF_ONE)
 void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source)
 {
 	uint8_t pll;
+#ifdef RAD1O
+	(void) source;
+	/* PLLA on XTAL */
+	pll = SI5351C_CLK_PLL_SRC_A;
+#endif
 
+#if (defined JAWBREAKER || defined HACKRF_ONE)
 	if (source == PLL_SOURCE_CLKIN) {
 		/* PLLB on CLKIN */
 		pll = SI5351C_CLK_PLL_SRC_B;
 	} else {
 		/* PLLA on XTAL */
 		pll = SI5351C_CLK_PLL_SRC_A;
 	}
-	uint8_t data[] = {16
-	,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
-	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
-	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
-	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
-	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA)
-	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
-	,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
-	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA)
-	 };
-	si5351c_write(drv, data, sizeof(data));
-}
 #endif
-
-#ifdef RAD1O
-void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll_sources source)
-{
-	(void) source;
-	uint8_t pll;
-
-	/* PLLA on XTAL */
-	pll = SI5351C_CLK_PLL_SRC_A;
-
 	/* Clock to CPU is deactivated as it is not used and creates noise */
 	/* External clock output is deactivated as it is not used and creates noise */
 	uint8_t data[] = {16
 	,SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
 	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
 	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_0_4) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA)
 	,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
-	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA)
+	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA) | SI5351C_CLK_INV
 	,SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(pll) | SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) | SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA)
 	,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
 	,SI5351C_CLK_POWERDOWN | SI5351C_CLK_INT_MODE /*not connected, but: plla int mode*/
 	 };
 	si5351c_write(drv, data, sizeof(data));
 }
-#endif
 
- void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
- {
-#ifdef RAD1O
+void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
+{
 	/* Enable CLK outputs 0, 1, 2, 4, 5 only. */
 	/* 7: Clock to CPU is deactivated as it is not used and creates noise */
-	/* 3: External clock output is deactivated as it is not used and creates noise */
+	/* 3: External clock output is deactivated by default */
 	uint8_t data[] = { 3, ~((1 << 0) | (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5))};
-#else
-	/* Enable CLK outputs 0, 1, 2, 3, 4, 5, 7 only. */
-	uint8_t data[] = { 3, 0x40 };
-#endif
- 	si5351c_write(drv, data, sizeof(data));
- }
-
+	si5351c_write(drv, data, sizeof(data));
+}
 
- void si5351c_set_int_mode(si5351c_driver_t* const drv, const uint_fast8_t ms_number, const uint_fast8_t on){
+void si5351c_set_int_mode(si5351c_driver_t* const drv, const uint_fast8_t ms_number, const uint_fast8_t on){
   uint8_t data[] = {16, 0};
 
   if(ms_number < 8){
@@ -244,8 +220,7 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv, const enum pll
 
       si5351c_write(drv, data, 2);
   }
-
- }
+}
 
 void si5351c_set_clock_source(si5351c_driver_t* const drv, const enum pll_sources source)
 {

firmware/cpld/sgpio_if/README.md

@@ -20,20 +20,6 @@ To build this VHDL project and produce an SVF file for flashing the CPLD:
 
 * Xilinx WebPACK 13.4 for Windows or Linux.
 
-To program the SVF file into the CPLD:
-
-* Dangerous Prototypes Bus Blaster v2:
-  * Configured with [JTAGKey buffers](http://dangerousprototypes.com/docs/Bus_Blaster_v2_buffer_logic).
-  * Connected to CPLD JTAG signals on Jellybean.
-
-* urJTAG built with libftdi support.
-
-* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
-  in the "Device Models" Support Resources section of the CoolRunner-II
-  Product Support & Documentation page. Only one file from the BSDL package is
-  required, and the "program" script below expects it to be at the relative
-  path "bsdl/xc2c/xc2c64.bsd".
-
 Generate an XSVF
 ================
 
@@ -56,8 +42,4 @@ After generating a programming file:
 To Program
 ==========
 
-./program
-
-...which connects to the Bus Blaster interface 0, sets the BSDL directory,
-detects devices on the JTAG chain, and writes the sgpio_if.svf file to the
-CPLD.
+$ hackrf_cpldjtag -x default.xsvf