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Remove last mentions of Jellybean
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dominicgs committed Feb 17, 2017
1 parent bc49bdc commit a4036ea
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Showing 10 changed files with 5 additions and 2,586 deletions.
34 changes: 0 additions & 34 deletions firmware/common/LPC4330_M4_memory.ld

This file was deleted.

10 changes: 4 additions & 6 deletions firmware/common/hackrf_core.c
Original file line number Diff line number Diff line change
Expand Up @@ -470,8 +470,7 @@ bool baseband_filter_bandwidth_set(const uint32_t bandwidth_hz) {
return bandwidth_hz_real != 0;
}

/* clock startup for Jellybean with Lemondrop attached
Configure PLL1 to max speed (204MHz).
/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
void cpu_clock_init(void)
{
Expand Down Expand Up @@ -546,7 +545,7 @@ void cpu_clock_init(void)
si5351c_write(&clock_gen, ms7data, sizeof(ms7data));
#endif

/* Set to 10 MHz, the common rate between Jellybean and Jawbreaker. */
/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
sample_rate_set(10000000);

si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
Expand All @@ -560,9 +559,8 @@ void cpu_clock_init(void)
i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);

/*
* 12MHz clock is entering LPC XTAL1/OSC input now. On
* Jellybean/Lemondrop, this is a signal from the clock generator. On
* Jawbreaker, there is a 12 MHz crystal at the LPC.
* 12MHz clock is entering LPC XTAL1/OSC input now.
* On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
* Set up PLL1 to run from XTAL1 input.
*/

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20 changes: 1 addition & 19 deletions firmware/cpld/sgpio_if/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -8,20 +8,6 @@ To build this VHDL project and produce an SVF file for flashing the CPLD:

* Xilinx WebPACK 13.4 for Windows or Linux.

To program the SVF file into the CPLD:

* Dangerous Prototypes Bus Blaster v2:
* Configured with [JTAGKey buffers](http://dangerousprototypes.com/docs/Bus_Blaster_v2_buffer_logic).
* Connected to CPLD JTAG signals on Jellybean.

* urJTAG built with libftdi support.

* BSDL model files for Xilinx CoolRunner-II XC264A, available at xilinx.com,
in the "Device Models" Support Resources section of the CoolRunner-II
Product Support & Documentation page. Only one file from the BSDL package is
required, and the "program" script below expects it to be at the relative
path "bsdl/xc2c/xc2c64.bsd".

Generate an XSVF
================

Expand All @@ -44,8 +30,4 @@ After generating a programming file:
To Program
==========

./program

...which connects to the Bus Blaster interface 0, sets the BSDL directory,
detects devices on the JTAG chain, and writes the sgpio_if.svf file to the
CPLD.
$ hackrf_cpldjtag -x default.xsvf
10 changes: 0 additions & 10 deletions firmware/cpld/sgpio_if/program

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37 changes: 0 additions & 37 deletions firmware/cpld/sgpio_if_passthrough/README.md

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10 changes: 0 additions & 10 deletions firmware/cpld/sgpio_if_passthrough/program

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