Change RFFC5071 clock from 40MHz to 50MHz and invert it

Now the MAX2837 and RFFC5071 clocks are out of phase with each other Hopefully this reduces some noise
doyke · Feb 22, 2017 · acaf0d1 · acaf0d1
1 parent 15ea074
commit acaf0d1
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Showing 2 changed files with 4 additions and 12 deletions.
diff --git a/firmware/common/hackrf_core.c b/firmware/common/hackrf_core.c
@@ -503,20 +503,12 @@ void cpu_clock_init(void)
 	 */
 
 	/* MS3/CLK3 is the source for the external clock output. */
-	si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
+	// si5351c_configure_multisynth(&clock_gen, 3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
 
-#if (defined JAWBREAKER || defined HACKRF_ONE)
-	/* MS4/CLK4 is the source for the RFFC5071 mixer. */
-	si5351c_configure_multisynth(&clock_gen, 4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
- 	/* MS5/CLK5 is the source for the MAX2837 clock input. */
-	si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
-#endif
-#ifdef RAD1O
-	/* MS4/CLK4 is the source for the MAX2837 clock input. */
+	/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
 	si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
-	/* MS5/CLK5 is the source for the RFFC5071 mixer. */
+ 	/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
 	si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
-#endif
 
 	/* MS6/CLK6 is unused. */
 	/* MS7/CLK7 is unused. */

diff --git a/firmware/common/rffc5071.c b/firmware/common/rffc5071.c
@@ -208,7 +208,7 @@ void rffc5071_enable(rffc5071_driver_t* const drv)  {
 }
 
 #define LO_MAX 5400
-#define REF_FREQ 50
+#define REF_FREQ 40
 #define FREQ_ONE_MHZ (1000*1000)
 
 /* configure frequency synthesizer in integer mode (lo in MHz) */