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synlig Public
Forked from chipsalliance/synligSystemVerilog synthesis tool
Verilog Apache License 2.0 UpdatedNov 26, 2024 -
verilator Public
Forked from verilator/verilatorVerilator open-source SystemVerilog simulator and lint system
C++ GNU Lesser General Public License v3.0 UpdatedNov 16, 2024 -
newlib Public
Forked from bminor/newlibUnofficial mirror of sourceware newlib repository. Updated daily.
C GNU General Public License v2.0 UpdatedNov 4, 2024 -
fusesoc-cores Public
Forked from fusesoc/fusesoc-coresFuseSoC standard core library
UpdatedNov 2, 2024 -
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woset-workshop.github.io Public
Forked from woset-workshop/woset-workshop.github.ioWorkshop on Open-Source EDA Technology (WOSET)
UpdatedOct 20, 2024 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedOct 11, 2024 -
openpiton Public
Forked from PrincetonUniversity/openpitonThe OpenPiton Platform
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yosys-slang Public
Forked from povik/yosys-slangslang-based frontend for Yosys
C++ ISC License UpdatedJun 12, 2024 -
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riscv-arch-test Public
Forked from riscv-non-isa/riscv-arch-testAssembly Apache License 2.0 UpdatedJun 3, 2024 -
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bsg_bladerunner Public
Forked from bespoke-silicon-group/bsg_bladerunnerMeta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
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bsg_replicant Public
Forked from bespoke-silicon-group/bsg_replicantBespoke Silicon Group AWS EC2 F1 Infrastructure and Interface logic for BSG Manycore
C BSD 3-Clause "New" or "Revised" License UpdatedOct 21, 2023 -
basejump_stl Public
Forked from bespoke-silicon-group/basejump_stlBaseJump STL: A Standard Template Library for SystemVerilog
Verilog Other UpdatedJul 20, 2023 -
ariane Public
Forked from openhwgroup/cva6Ariane is a 6-stage RISC-V CPU capable of booting Linux
C++ Other UpdatedJun 19, 2023 -
skywater-pdk-libs-sky130_fd_sc_hd Public
Forked from google/skywater-pdk-libs-sky130_fd_sc_hd"High density" digital standard cells for SKY130 provided by SkyWater.
Verilog Apache License 2.0 UpdatedFeb 22, 2023 -
riscv-dv Public
Forked from chipsalliance/riscv-dvSystemVerilog Apache License 2.0 UpdatedFeb 17, 2023 -
axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedFeb 10, 2023 -
fossi-foundation.github.io Public
Forked from fossi-foundation/fossi-foundation.github.ioFOSSi Foundation Website
HTML UpdatedFeb 7, 2023 -
riscv-gcc Public
Forked from bespoke-silicon-group/riscv-gccC GNU General Public License v2.0 UpdatedJan 5, 2023 -
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rocket-chip Public
Forked from chipsalliance/rocket-chipRocket Chip Generator
Scala Other UpdatedSep 8, 2022 -
bsg_sv2v Public
Forked from bespoke-silicon-group/bsg_sv2vPython BSD 3-Clause "New" or "Revised" License UpdatedMar 31, 2022 -
Surelog Public
Forked from chipsalliance/SurelogSystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
C++ Apache License 2.0 UpdatedJan 18, 2022 -
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openc910 Public
Forked from XUANTIE-RV/openc910OpenXuantie - OpenC910 Core
Verilog Apache License 2.0 UpdatedOct 19, 2021