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diff --git a/README.md b/README.md
diff --git a/afifo.v b/afifo.v
diff --git a/ahb_protocal.md b/ahb_protocal.md
@@ -1,4 +1,10 @@
-# AHB协议学习笔记
+---
+title: AHB协议学习笔记
+date: 2018-12-12 22:50:15
+tags: [AMBA, SOC]
+category: SOC设计
+toc_number: false
+---
 
 ## 1. AHB组成部分
 * AHB主设备(master)
@@ -13,7 +19,9 @@
 * AHB译码器(decoder)
   - 通过地址译码来决定选择哪个slave
 
-![](assets/markdown-img-paste-20181128135549530.png)
+![AHB总线结构图](assets/markdown-img-paste-20181128135549530.png)
+
+<!-- more -->
 
 ## 2. AHB信号
 | Name              | Source           | To                           | Desciption                                                                                                                                              |
@@ -121,9 +129,10 @@ config: {hscale: 3}
 * INCR传输HADDR累加值与HSIZE有关，每次加2^HSIZE^
 * Burst传输不能跨越1K边界，即到达1K边界需要用NONSEQ发起一次新的传输
 
-**思考：为什么burst传输不能跨越1K边界？**
+:::hint info 
+**:question:思考：为什么burst传输不能跨越1K边界？**
 ARM的回答：The 1KB restriction you refer to is not a restriction on maximum slave size but a constraint within AHB that says that a burst must not cross a 1KB boundary. The limit is designed to prevent bursts crossing from one device to another and to give a reasonable trade-off between burst size and efficiency. In practise, this means that a master must ALWAYS break a burst that would otherwise cross the 1KB boundary and restart it with a non-sequential transfer.
-
+:::
 
 ```wavedrom
 {signal: [
@@ -158,11 +167,14 @@ config: {hscale: 3}
 ```
 
 ### 4.4 WRAP传输
-**思考：如何确定WRAP边界？**
+::: hint info 
+**:question:思考：如何确定WRAP边界？**
 wrap的边界与HSIZE和HBURST都有关系，对于WRAP4来说，HADDR[HSIZE+1:HSIZE]==2'b11就是边界；对于WRAP8来说，HADDR[HSIZE+2:HSIZE]==2'b111就是边界，同理适用于WRAP16。
 **假如**：HSIZE=3'b010时，HADDR起始地址为0x48
 **当HBURST为WRAP4时**，HADDR依次为0x48 -> 0x4C -> 0x40 -> 0x44(对应的HADDR[3:2]依次为2'b10 -> 2'b11 -> 2'b00 -> 2'b01)
 **当HBURST为WRAP8时**，HADDR依次为0x48 -> 0x4C -> 0x50 -> 0x54 -> 0x58 -> 0x5C -> 0x40 -> 0x44(对应的HADDR[4:2]依次为3'b010 -> 3'b011 -> 3'b100 -> 3'b101 -> 3'b110 -> 3'b111 -> 3'b000 -> 3'b001)
+:::
+
 
 ```wavedrom
 {signal: [

diff --git a/asic_design_example.md b/asic_design_example.md
@@ -1,8 +1,15 @@
-# ASIC设计经典笔试题收录
+---
+title: ASIC设计经典笔试题收录
+date: 2018-09-26 22:50:15
+tags: [面试, ASIC]
+category: ASIC设计
+---
 
 ## 时序优化题
 <font color="red">问</font>：CLK->Q的时间为0.5ns，组合逻辑cm0、cm1延时均为7ns，在不增加流水线数目(pipeline stage)的前提下，怎么修改电路，才能让CLK达到100MHZ？(提示：C宽为2bit)
-![](assets/markdown-img-paste-20180923141559401.png)
+![时序优化前](assets/markdown-img-paste-20180923141559401.png)
+
+<!-- more -->
 
 <font color="blue">答</font>：放置4个cm1，分别用定值00、01、10、11作为输入，在D前放置4-to-1 Mux，将cm0输出作为选择信号，目的是将cm1的7ns替换为Mux Cell的延时。(逻辑复制，面积换时间)
-![](assets/markdown-img-paste-20180923142133179.png)
+![时序优化后](assets/markdown-img-paste-20180923142133179.png)
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diff --git a/common_links.md b/common_links.md
diff --git a/compile_env.md b/compile_env.md
@@ -0,0 +1,48 @@
+---
+title: 搭建irun编译与起verdi小环境
+date: 2019-05-04 22:30:02
+tags: [eda_tools, ASIC]
+category: eda_tools
+---
+
+## 1. 小环境makefile模板
+```makefile
+design = tb
+verilog_flist = -f ./test.vc tb.v
+vhd_flist =
+wave = wave.fsdb
+
+#whether to open verdi wave gui
+ifdef wave
+	verdi_cmd += -ssf $(wave)
+endif
+
+.PHONY: help clean ius compile verdi
+
+help:
+	@echo "#==============================================================="
+	@echo "# [Info] make help    : show help infomation"   
+	@echo "# [Info] make clean   : clean ius and verdi compile library,log"   
+	@echo "# [Info] make compile : compile for verdi"   
+	@echo "# [Info] make verdi   : raise verdi gui"   
+	@echo "#==============================================================="
+
+clean:
+	@rm chip_lib.lib++ work.lib++ INCA_libs verdiLog vericomLog vhdlcomLog -rf
+
+ius:
+	irun +access+wr -smartorder -clean -ntcnotchks -V93 -vtimescale 1ns/1ps +define+RD=1 -work chip_lib $(verilog_flist) $(vhd_flist) -top $(design) -64bit
+
+compile:
+ifdef vhdl_flist
+	vhdlcom -V93 -sup_sem_error -smartorder -work chip_lib $(vhdl_flist)
+endif
+ifdef verilog_flist
+	vericom -sv +systemverilog+sv +v95ext+v95 +verilog2001ext+v -ignorekwd_config +define+RD=1  -work chip_lib $(verilog_flist)
+endif
+
+verdi:compile
+	verdi -lib chip_lib $(verdi_cmd) &
+```
+
+<!-- more -->
diff --git a/eda_irun.md b/eda_irun.md
@@ -1,4 +1,9 @@
-# EDA工具使用
+---
+title: EDA工具使用 
+date: 2018-09-25 20:46:02
+tags: [eda_tools, ASIC]
+category: eda_tools
+---
 
 ## cadence irun命令
 ### 常用编译
@@ -17,6 +22,8 @@ set_covergroup -per_instance_default_one
 select_coverage -all -instance tb_top.xxx*...
 ```
 
+<!-- more -->
+
 ## Synopsys Verdi
 ```shell
 vhdlcom -v93 -sup_sem_error -smartorder -work chip_lib -f vhdl.flist

diff --git a/education_book.md b/education_book.md
@@ -1,4 +1,9 @@
-# 孩子教养推荐书籍
+---
+title: 孩子教养推荐书籍
+date: 2018-09-23 22:50:15
+tags: [儿童教育, 书籍]
+category: 教育
+---
 
 1. 父母效能训练手册
  9.1 (583人评价)
@@ -14,6 +19,8 @@
 出版年: 2009-1
 评语：挺精彩。以阿德勒理论为基础
 
+<!-- more -->
+
 3. 培养高情商的孩子
  8.5 (243人评价)
 作者: 约翰 戈特曼