TODO
- imem设计有问题，需加一级流水重构
- 设计verilator TopSim
- 加Difftest
- 写论文，鸽一阵
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RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
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dzwduan/ridecore
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RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
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- Verilog 98.0%
- SystemVerilog 2.0%