fix whiteline bug and clean code

[simondona]

The output files had problems with FastCap2 due to a white line. Moreover the two big functions have been merged because they were sharing most of the code: now the code should be easier to maintain.

[ediloren]

Hi Simone

thanks for the pull request. I'm reviewing the commits before merging. What is the issue with the whiteline in FastCap2? Actually there should be no issue (even if the code had been actually written to produce an input file for FasterCap, not for FastCap2: dielectric in/out definitions are per-panel references, as finding a common reference point for an arbitrary group of panels forming a dielectric interface is a more challenging task)

Enrico

[simondona]

Hi Enrico, sorry for the huge delay.
I just tried to reproduce the issue. Compiled FastCap2 (https://github.com/ediloren/FastCap2) from the branch WRCad on Debian testing.
After exporting a mesh with the current EM-Workbench-for-FreeCAD code, calling fastcap mymesh.txt gives me the following error:

Running ./fastcap 2.0wr (18Sep92, rev 070714)
  Input: mymesh.txt
quickif: bad line format, line 3:

By deleting the white line on line 3 the simulation runs correctly.

Simone

[ediloren]

Ciao Simone, no problem - but now I understand your issue, and will look into it. Actually the EM workbench simple proof of concept was designed to generate input files for FasterCap, not FastCap, but should work anyway, at least for conductor definitions. However the WR Cad branch may behave a bit differently - this has been modified by Steve by WRCad, and not directly by us. We are anyway proceeding towards a more complete workbench, in steps of course, leveraging the flexibility of FreeCAD. You will see the commits in github as soon as there is something stable enough. Grazie, Enrico Enrico Di Lorenzo General Manager Phone: +39.349.6114040 Skype: enrico.dilorenzo.nounderscore mailto: [email protected] FastFieldSolvers S.R.L. Via de Castillia, 7 - 20871 Vimercate (MB) Italy Numero REA / REA number: MB - 1885192 P.IVA/VAT No. IT 07931440965 http://www.fastfieldsolvers.com From: "Simone Donadello" [email protected] To: "ediloren/EM-Workbench-for-FreeCAD" [email protected] Cc: "ediloren" [email protected],"Comment" [email protected] Date: Fri, 05 Jan 2018 11:05:09 -0800 Subject: Re: [ediloren/EM-Workbench-for-FreeCAD] fix whiteline bug and clean code (#1) Hi Enrico, sorry for the huge delay. I just tried to reproduce the issue. Compiled FastCap2 (https://github.com/ediloren/FastCap2) from the branch WRCad on Debian testing. After exporting a mesh with the current EM-Workbench-for-FreeCAD code, calling fastcap mesh.txt gives me the following error: Running ./fastcap 2.0wr (18Sep92, rev 070714) Input: mymesh.txt quickif: bad line format, line 3: By deleting the white line on line 3 the simulation runs correctly. Simone — You are receiving this because you commented. Reply to this email directly, view it on GitHub, or mute the thread.

[simondona]

Ok, now I understand, thank you!
Ciao
Simone