Merge branch 'dev'

eepro-bt · Jan 19, 2020 · c2c7113 · c2c7113
2 parents dbec0fe + b98ad44
commit c2c7113
Show file tree

Hide file tree

Showing 62 changed files with 530 additions and 0 deletions.
diff --git a/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141029901.png b/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141029901.png
diff --git a/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141106799.png b/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141106799.png
diff --git a/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141328543.png b/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141328543.png
diff --git a/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141429408.png b/vitis_by_zcu102_0_建立开发环境.assets/image-20200108141429408.png
diff --git a/vitis_by_zcu102_0_建立开发环境.md b/vitis_by_zcu102_0_建立开发环境.md
@@ -0,0 +1,87 @@
+# 前言
+
+Vitis 被 Xilinx 称为 “统一软件平台”，从目前已了解的情况来看，嵌入式软件开发在 Vitis 上更为简单方便。
+
+从 ISE 到 Vivado，再到 Vitis 的升级趋势来看，Vitis 将是未来数年的开发主力。
+
+虽然 2019.2 的首发版本可能会有许多 bug，但是试用 Vitis 已足够。
+
+**Vitis by ZCU102** 系列文章将在 zcu102 开发板上尽可能试用 Vitis Embedded 的各种功能。
+
+主要参考的官方文档包括：
+
+- ug1400
+- ug1209
+- ug1165
+- ug1393
+
+# 开发环境
+
+硬件环境：zcu102 开发板
+
+软件环境：ubuntu 18.04.3、Vitis 2019.2.1
+
+虽然 ug1400 中只提及支持 ubuntu 18.04.2，但是以下所有内容都基于 18.04.3 版本。
+
+注意：根据 ug1400 的说明 Windows 系统对 Vitis 的嵌入式开发不能完全支持
+
+>  Note: Windows OS support is limited to the Vitis embedded software development flow.
+
+# 安装步骤
+
+## 安装 opencl
+
+>  sudo apt-get update
+>
+>  sudo apt-get install ocl-icd-libopencl1 opencl-headers ocl-icd-opencl-dev
+
+## 下载并安装 Vitis Software Platform
+
+以下网页日期为 20200108
+
+进入 [Xilinx 中国网站](https://china.xilinx.com/)
+
+打开 [Vitis 统一软件平台](https://china.xilinx.com/products/design-tools/vitis/vitis-platform.html)
+
+![image-20200108141029901](vitis_by_zcu102_0_%E5%BB%BA%E7%AB%8B%E5%BC%80%E5%8F%91%E7%8E%AF%E5%A2%83.assets/image-20200108141029901.png)
+
+进入 [立即下载]()
+
+![image-20200108141106799](vitis_by_zcu102_0_%E5%BB%BA%E7%AB%8B%E5%BC%80%E5%8F%91%E7%8E%AF%E5%A2%83.assets/image-20200108141106799.png)
+
+选择 **Vitis(软件开发者)**页面最下端的离线安装包
+
+![image-20200108141328543](vitis_by_zcu102_0_%E5%BB%BA%E7%AB%8B%E5%BC%80%E5%8F%91%E7%8E%AF%E5%A2%83.assets/image-20200108141328543.png)
+
+以及页面最上端的更新包
+
+![image-20200108141429408](vitis_by_zcu102_0_%E5%BB%BA%E7%AB%8B%E5%BC%80%E5%8F%91%E7%8E%AF%E5%A2%83.assets/image-20200108141429408.png)
+
+使用 Xilinx 账号下载解压，并且根据提示按照正常流程安装。**注意：安装过程中应当勾选所有可安装组件。**
+
+## 安装加载线驱动
+
+参考 ug973 的 Install Cable Driver 部分的说明。
+
+>  cd 
+>  <Vivado Install Dir>/data/xicom/cable_drivers/lin64/
+>
+>  install_script/install_drivers/
+>
+>  sudo ./install_drivers
+
+完成安装后 Terminal 显示
+
+>  INFO: Driver installation successful.
+
+## 安装 Xilinx Runtime (XRT)
+
+根据 ug1400 的说明[下载 XRT](https://www.xilinx.com/bin/public/openDownload?filename=xrt_201920.2.3.1301_18.04-xrt.deb) 并安装
+
+>  sudo apt install <deb-dir>/<xrt_filename_OS>.deb
+
+## 设置运行路径
+
+>source <VITIS_INSTALL_DIR>/Vitis/2019.2/settings64.sh
+>
+>source <XRT_INSTALL_DIR>/xilinx/xrt/setup.sh
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200108144701256.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200108144701256.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109072120445.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109072120445.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109072608859.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109072608859.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109072714562.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109072714562.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109073010314.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109073010314.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109073349266.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109073349266.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109073710872.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109073710872.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075511983.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075511983.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075649729.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075649729.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075729098.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075729098.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075808052.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075808052.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075923553.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109075923553.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109080011539.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109080011539.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109080409969.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109080409969.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109080629118.png b/vitis_by_zcu102_1_Hello Vitis.assets/image-20200109080629118.png
diff --git a/vitis_by_zcu102_1_Hello Vitis.md b/vitis_by_zcu102_1_Hello Vitis.md
@@ -0,0 +1,89 @@
+主要参考：ug1400
+
+# 安装串口调试软件
+
+安装串口软件 [tinyserial](https://github.com/lifimlt/tinyserial/releases)
+
+![image-20200108144701256](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200108144701256.png)
+
+本人**使用 Qt 5.12.6 编译**后使用（deb 安装后无法运行）。
+
+# 建立 Platform Project
+
+启动 Vitis Software Platform，设置 Workspace 路径后点击 Launch 按钮。
+
+![image-20200109072120445](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109072120445.png)
+
+进入 IDE 后在菜单栏选择 File > New > Platform Project
+
+设置 Project name 后点击 Next 按钮
+
+![image-20200109072608859](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109072608859.png)
+
+选中 Create from hardware specification (XSA) 后，点击 Next 按钮
+
+![image-20200109072714562](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109072714562.png)
+
+点击 Browse 按钮后在以下路径选择 zcu102 的默认 XSA 文件
+
+选择 Operating system 为 standalone
+
+选择 Processor 为 psu_cortexa53_0
+
+点击 Finish 按钮
+
+![image-20200109073010314](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109073010314.png)
+
+进入 Eclipse 的 Desgin 界面
+
+![image-20200109073349266](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109073349266.png)
+
+在 zcu102_platform 工程打开右键菜单选择 Build Project
+
+完成后显示
+
+![image-20200109073710872](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109073710872.png)
+
+# 建立 Application Project
+
+在菜单栏选择 File > New > Application Project
+
+弹出窗口中设置工程名称，然后点击 Next 按钮
+
+![image-20200109075511983](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109075511983.png)
+
+选中之前建立的 Platform Project，然后点击 Next 按钮
+
+![image-20200109075649729](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109075649729.png)
+
+接下来的页面保持默认，点击 Next 按钮
+
+![image-20200109075729098](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109075729098.png)
+
+选中 Hello World 模板后点击 Finish 按钮
+
+![image-20200109075808052](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109075808052.png)
+
+在 Explorer 中出现 hello 工程，双击打开 helloworld.c
+
+![image-20200109075923553](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109075923553.png)
+
+修改原始代码为框内代码
+
+![image-20200109080011539](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109080011539.png)
+
+在 hello 工程的右键菜单中选择 Build Project
+
+# 验证
+
+连接 zcu102 板卡的 JTAG 线和 UART 转 USB 线至主机后给板卡上电
+
+打开 tinyserial 软件，按下图配置并且点击 open 按钮
+
+![image-20200109080409969](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109080409969.png)
+
+在 hello 工程的右键菜单中选择 Run As > Launch on Hardware (Single Application Debug)
+
+在 tinyserial 中收到 Hello Vitis 的串口数据
+
+![image-20200109080629118](vitis_by_zcu102_1_Hello%20Vitis.assets/image-20200109080629118.png)
diff --git a/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109072120445-1579066313985.png b/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109072120445-1579066313985.png
diff --git a/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109072608859-1579066313986.png b/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109072608859-1579066313986.png
diff --git a/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109072714562-1579066345973.png b/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109072714562-1579066345973.png
diff --git a/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109075511983-1579067746278.png b/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109075511983-1579067746278.png
diff --git a/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109075729098-1579067746279.png b/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109075729098-1579067746279.png
diff --git a/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109075808052-1579067746279.png b/...cu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200109075808052-1579067746279.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115092917242.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115092917242.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115093227375.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115093227375.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115093557195.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115093557195.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115094207894.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115094207894.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115132948002.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115132948002.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115133659435.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115133659435.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115133813292.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115133813292.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115134130829.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115134130829.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115135645854.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115135645854.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115135821935.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115135821935.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140038838.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140038838.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140133244.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140133244.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140326866.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140326866.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140639961.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140639961.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140816369.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115140816369.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115142928843.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115142928843.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115143301942.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115143301942.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115143449670.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115143449670.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115143804628.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115143804628.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115144144301.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115144144301.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115144208589.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115144208589.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115144325869.png b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.assets/image-20200115144325869.png
diff --git a/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.md b/vitis_by_zcu102_2_Vitis 实现 Bare-Metal 工程.md
@@ -0,0 +1,168 @@
+具体方法与 SDK 的 Bare-metal 工程基本一致，详细操作可以参考 [zcu102 系列文档]()。
+
+## 建立 Vivado 工程
+
+建立基于 zcu102 开发板的 Vivado 工程。
+
+建立 Block Design，添加 Zynq UltraScale+ MPSoc 的 IP
+
+ ![image-20200115092917242](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115092917242.png)
+
+点击 Run Block Automation，自动配置 IP 模块。
+
+双击打开配置窗口查看 UART 0 和 UART 1 已按照 zcu102 开发板的硬件连接设置完成。
+
+![image-20200115093227375](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115093227375.png)
+
+并且在 PS-PL Configuration 页关闭 AXI HPM0 FPD 和 AXI HPM1 FPD
+
+![image-20200115093557195](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115093557195.png)
+
+保存 Block Design，Generate Output Products 并且 Create HDL Wrapper，完成后 Sources 窗口如下：
+
+![image-20200115094207894](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115094207894.png)
+
+在 Flow Navigator 中选择 Generate Bitstream，等待运行结束。
+
+在 Vivado 菜单栏选择 File > Export > Export Hardware，选中 Include Bitstream，点击 OK 按钮。
+
+![image-20200115132948002](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115132948002.png)
+
+导出完成后在 Export to 路径下出现导出的 xsa 文件：
+
+![image-20200115133659435](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115133659435.png)
+
+## 建立 Platform Project
+
+启动 Vitis Software Platform，设置 Workspace 路径后点击 Launch 按钮。
+
+![image-20200109072120445](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200109072120445-1579066313985.png)
+
+进入 IDE 后在菜单栏选择 File > New > Platform Project
+
+设置 Project name 后点击 Next 按钮
+
+![image-20200109072608859](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200109072608859-1579066313986.png)
+
+选中 Create from hardware specification (XSA) 后，点击 Next 按钮
+
+![image-20200109072714562](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200109072714562-1579066345973.png)
+
+点击 Browse 按钮，选中由 Vivado 工程导出的 xsa 文件
+
+选择 Operating system 为 standlone
+
+选择 Processor 为 psu_cortexa53_0
+
+点击 Finish 按钮
+
+![image-20200115133813292](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115133813292.png)
+
+关闭默认的 Welcome 界面，在 Explorer 中的工程上右键点击，打开菜单选择 Build Project
+
+![image-20200115134130829](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115134130829.png)
+
+## 建立 Application Project
+
+在菜单栏选择 File > New > Application Project
+
+弹出窗口中设置工程名称，然后点击 Next 按钮
+
+![image-20200109075511983](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200109075511983-1579067746278.png)
+
+选中之前建立的 Platform Project，然后点击 Next 按钮
+
+![image-20200115135645854](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115135645854.png)
+
+接下来的页面保持默认，点击 Next 按钮
+
+![image-20200109075729098](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200109075729098-1579067746279.png)
+
+选中 Hello World 模板后点击 Finish 按钮
+
+![image-20200109075808052](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200109075808052-1579067746279.png)
+
+在 Explorer 中出现 hello 工程，双击打开 helloworld.c
+
+![image-20200115135821935](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115135821935.png)
+
+修改原始代码为下方代码
+
+```c
+#include <stdio.h>
+#include "platform.h"
+#include "xil_printf.h"
+
+
+int main()
+{
+ init_platform();
+
+ print("Hello Uart\n\r");
+
+ cleanup_platform();
+ return 0;
+}
+```
+
+## 运行测试
+
+双击打开 Platform Project 中的 platform.spr
+
+![image-20200115140038838](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115140038838.png)
+
+选中当前 a53 的 Board Support Package，在页面内点击 Modify BSP Settings... 按钮
+
+![image-20200115140133244](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115140133244.png)
+
+在弹出配置窗口的 standalone 页面选择 stdout 为 psu_uart_0，或者 psu_uart_1
+
+![image-20200115140326866](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115140326866.png)
+
+重新 Build Platform Project
+
+在 Application Project 的右键菜单选择 Build Project
+
+板卡上电并且打开 TinySerial，打开 ttyUSB0 串口
+
+![image-20200115140639961](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115140639961.png)
+
+在 Application Project 的右键菜单选择 Run As > Launch on Hardware
+
+在 TinySerial 中收到 Hello Uart
+
+![image-20200115140816369](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115140816369.png)
+
+同样的方法测试 uart_1。
+
+在 BSP Settings 中选中 stdout 为 psu_uart_1，在 TinySerial 中打开 ttyUSB1 串口，却发现串口打开失败，于是用查看串口状态
+
+![image-20200115142928843](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115142928843.png)
+
+原来是 ttyUSB1 权限设置问题，于是修改权限：
+
+![image-20200115143301942](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115143301942.png)
+
+TinySerial 中打开成功后运行 Vitis Application
+
+![image-20200115143449670](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115143449670.png)
+
+发现未收到 FSBL 的信息，原因是 FSBL 的 BSP 设置为 uart_0 的 stdout，使用 2 个 TinySerial 程序分别打开 ttyUSB0 和 ttyUSB1，再次运行 Vitis Application：
+
+![image-20200115143804628](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115143804628.png)
+
+## Vitis 自带的串口 Terminal
+
+在 Vitis 菜单中选择 Window > Show View > Xilinx/Vitis Serial Terminal
+
+在界面上点击 + 号按钮连接串口（旁边的 x 按钮用于关闭当前串口）
+
+![image-20200115144144301](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115144144301.png)
+
+在弹出窗口中配置串口
+
+![image-20200115144208589](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115144208589.png)
+
+按前述办法运行 Vitis Application，Vitis Serial Terminal 收到正确的数据
+
+![image-20200115144325869](vitis_by_zcu102_2_Vitis%20%E5%AE%9E%E7%8E%B0%20Bare-Metal%20%E5%B7%A5%E7%A8%8B.assets/image-20200115144325869.png)
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119104127247.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119104127247.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119104428781.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119104428781.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110131026.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110131026.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110411544.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110411544.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110538790.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110538790.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110627045.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119110627045.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111055656.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111055656.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111412100.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111412100.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111528874.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111528874.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111944619.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119111944619.png
diff --git a/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119112832427.png b/vitis_by_zcu102_2_Vitis 实现多核工作.assets/image-20200119112832427.png