fixing uvm item name to bus_item instead of bus_bus_item

efabless · Mar 7, 2024 · 8050a22 · 8050a22
1 parent 81b86e7
commit 8050a22
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Showing 8 changed files with 11 additions and 11 deletions.
diff --git a/verify/uvm-python/ref_model/ref_model.py b/verify/uvm-python/ref_model/ref_model.py
@@ -6,7 +6,7 @@
 from uvm.base.uvm_config_db import UVMConfigDb
 from uvm.tlm1.uvm_analysis_port import UVMAnalysisExport
 from EF_UVM.ref_model.ref_model import ref_model
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from tmr32_item.tmr32_item import tmr32_pwm_item
 from EF_UVM.ip_env.ip_agent.ip_monitor import ip_monitor
 from cocotb.triggers import Timer, ClockCycles, FallingEdge, Event, RisingEdge, Combine, First
@@ -46,11 +46,11 @@ def write_bus(self, tr):
             uvm_info("vip", "reset from the vip", UVM_LOW)
             self.regs.write_reg_value("CTRL", 0, force_write=True)
             return
-        if tr.kind == bus_bus_item.WRITE:
+        if tr.kind == bus_item.WRITE:
             self.bus_write_event.set()
             self.regs.write_reg_value(tr.addr, tr.data)
             self.bus_bus_export.write(tr)
-        elif tr.kind == bus_bus_item.READ:
+        elif tr.kind == bus_item.READ:
             if tr.addr == self.regs.reg_name_to_address["TMR"] and not self._timer_first_flag:
                 # calibrate the timer
                 self._timer_first_flag = True

diff --git a/verify/uvm-python/tmr32_coverage/tmr32_bus_coverage.py b/verify/uvm-python/tmr32_coverage/tmr32_bus_coverage.py
@@ -7,7 +7,7 @@
 from uvm.macros.uvm_tlm_defines import uvm_analysis_imp_decl
 from EF_UVM.ip_env.ip_coverage.ip_coverage import ip_coverage
 from EF_UVM.bus_env.bus_coverage.bus_coverage import bus_coverage
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from cocotb_coverage.coverage import CoverPoint, CoverCross
 
 
@@ -24,7 +24,7 @@ def build_phase(self, phase):
 
     def write_bus(self, tr):
         super().write_bus(tr)
-        if tr.kind == bus_bus_item.READ and tr.addr == 0x00: # read from tmr val 
+        if tr.kind == bus_item.READ and tr.addr == 0x00: # read from tmr val 
             self.timer_cov_groups.sample_timer(tr)
 
 uvm_component_utils(tmr32_bus_coverage)

diff --git a/verify/uvm-python/tmr32_seq_lib/pwm_actions_seq.py b/verify/uvm-python/tmr32_seq_lib/pwm_actions_seq.py
@@ -1,7 +1,7 @@
 from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_fatal
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from uvm.base.uvm_config_db import UVMConfigDb
 from cocotb.triggers import Timer
 from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do

diff --git a/verify/uvm-python/tmr32_seq_lib/pwm_pr_seq.py b/verify/uvm-python/tmr32_seq_lib/pwm_pr_seq.py
@@ -1,7 +1,7 @@
 from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_fatal
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from uvm.base.uvm_config_db import UVMConfigDb
 from cocotb.triggers import Timer
 from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do

diff --git a/verify/uvm-python/tmr32_seq_lib/pwm_tmr_seq.py b/verify/uvm-python/tmr32_seq_lib/pwm_tmr_seq.py
@@ -1,7 +1,7 @@
 from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_fatal
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from uvm.base.uvm_config_db import UVMConfigDb
 from cocotb.triggers import Timer
 from uvm.macros.uvm_sequence_defines import uvm_do_with, uvm_do

diff --git a/verify/uvm-python/tmr32_seq_lib/temp.py b/verify/uvm-python/tmr32_seq_lib/temp.py
@@ -1,7 +1,7 @@
 from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_fatal
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from uvm.base.uvm_config_db import UVMConfigDb
 from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
 from cocotb.triggers import Timer

diff --git a/verify/uvm-python/tmr32_seq_lib/timer_config.py b/verify/uvm-python/tmr32_seq_lib/timer_config.py
@@ -1,7 +1,7 @@
 from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_fatal
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from uvm.base.uvm_config_db import UVMConfigDb
 from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
 from cocotb.triggers import Timer

diff --git a/verify/uvm-python/tmr32_seq_lib/timer_val.py b/verify/uvm-python/tmr32_seq_lib/timer_val.py
@@ -1,7 +1,7 @@
 from uvm.seq import UVMSequence
 from uvm.macros.uvm_object_defines import uvm_object_utils
 from uvm.macros.uvm_message_defines import uvm_fatal
-from EF_UVM.bus_env.bus_item import bus_bus_item
+from EF_UVM.bus_env.bus_item import bus_item
 from uvm.base.uvm_config_db import UVMConfigDb
 from EF_UVM.bus_env.bus_seq_lib.bus_seq_base import bus_seq_base
 from cocotb.triggers import Timer