Updates to mapper (lsils#484)

* Technology mapper

* Tech mapper fixes

* Tech mapper test updates

* Updates and fixes

* Mapper updates: switching power optimization and templates restructuring

* Mapper: added option to exploit logic sharing, name modifications, tests and experiments updates

* minor fixes

* Modified test: from exact_map to map

* Added P-enumeration and N-matching option in library and mapping to support bigger cell libraries, improved mapping performances, fixed error when truth table minimization is false, increased the cut limit to 50, updated tests for changes

* Added inverter usage in exact mapping

* removed always_inline to avoid compiler error on Windows

* Added mapper documentation

* docs fix

docs/algorithms/cut_enumeration.rst

@@ -97,7 +97,16 @@ Pre-defined cut types
 
 .. doxygenstruct:: mockturtle::cut_enumeration_spectr_cut
 
+**Header:** ``mockturtle/algorithms/cut_enumeration/tech_map_cut.hpp``
+
+.. doxygenstruct:: mockturtle::cut_enumeration_tech_map_cut
+
+**Header:** ``mockturtle/algorithms/cut_enumeration/exact_map_cut.hpp``
+
+.. doxygenstruct:: mockturtle::cut_enumeration_exact_map_cut
+
 Special-purpose implementations
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. doxygenfunction:: mockturtle::fast_cut_enumeration
 
 .. doxygenfunction:: mockturtle::fast_small_cut_enumeration

docs/algorithms/mapper.rst

@@ -0,0 +1,78 @@
+Mapper
+------
+
+**Header:** ``mockturtle/algorithms/mapper.hpp``
+
+A versatile mapper that supports technology mapping and graph mapping.
+The mapper is independent of the underlying graph representation. Hence,
+it supports generic subject graph representations (e.g., AIG, and MIG)
+and a generic target representation (e.g. cell library, XMG).
+The mapper aims at finding a good mapping with respect to delay, area,
+and switching power.
+
+The mapper uses a library (hash table) to facilitate Boolean matching.
+For technology mapping, it needs `tech_library` while for graph mapping
+it needs `exact_library`. For technology mapping, the generation of both NP- and
+P-configurations of gates are supported. Generally, it is convenient to use
+NP-configurations for small cell libraries (<20 gates). For bigger libraries,
+P-configurations perform better. For graph mapping, NPN classification is used
+instead.
+
+The following example shows how to perform delay-oriented technology mapping
+from an And-inverter graph using the default settings:
+
+.. code-block:: c++
+
+ aig_network aig = ...;
+
+ /* read cell library in genlib format */
+ std::vector<gate> gates;
+ std::ifstream in( ... );
+ lorina::read_genlib( in, genlib_reader( gates ) )
+ tech_library tech_lib( gates );
+
+ /* perform technology mapping */
+ klut_network res = map( aig, tech_lib );
+
+The mapped network is returned as a k-LUT network in which each k-LUT
+abstracts a cell.
+
+The next example performs area-oriented graph mapping from AIG to MIG
+using a NPN resynthesis database of structures:
+
+.. code-block:: c++
+
+ aig_network aig = ...;
+
+ /* load the npn database in the library */
+ mig_npn_resynthesis resyn{ true };
+ exact_library<mig_network, mig_npn_resynthesis> exact_lib( resyn );
+
+ /* perform graph mapping */
+ map_params ps;
+ ps.skip_delay_round = true;
+ ps.required_time = std::numeric_limits<double>::max();
+ mig_network res = map( aig, exact_lib, ps );
+
+For graph mapping, we suggest reading the network directly in the
+target graph representation if possible (e.g. read an AIG as a MIG)
+since the mapping often leads to better results in this setting.
+
+As a default setting, cut enumeration minimizes the truth tables.
+This helps improving the results but slows down the computation. For
+a faster mapping set the truth table minimization parameter to false.
+The maximum number of cuts stored for each node is limited to 49.
+To increase this limit, change `max_cut_num` in `fast_network_cuts`.
+
+**Parameters and statistics**
+
+.. doxygenstruct:: mockturtle::map_params
+ :members:
+
+.. doxygenstruct:: mockturtle::map_stats
+ :members:
+
+**Algorithm**
+
+.. doxygenfunction:: mockturtle::map(Ntk const&, tech_library<NInputs, Configuration> const&, map_params const&, map_stats*)
+.. doxygenfunction:: mockturtle::map(Ntk&, exact_library<NtkDest, RewritingFn, NInputs> const&, map_params const&, map_stats*)

docs/index.rst

@@ -27,6 +27,7 @@ Welcome to mockturtle's documentation!
  :maxdepth: 2
  :caption: Algorithms
 
+ algorithms/mapper
  algorithms/lut_mapping
  algorithms/collapse_mapped
  algorithms/node_resynthesis

docs/utils/util_data_structures.rst

@@ -34,6 +34,37 @@ Node map
 
 .. doxygenfunction:: mockturtle::initialize_copy_network
 
+Tech Library
+~~~~~~~~~~~~
+
+**Header:** ``mockturtle/utils/tech_library.hpp``
+
+.. doc_overview_table:: classmockturtle_1_1tech__library
+ :column: Method
+
+ get_supergates
+ get_inverter_info
+ max_gate_size
+ get_gates
+
+.. doxygenclass:: mockturtle::tech_library
+ :members:
+
+Exact Library
+~~~~~~~~~~~~~
+
+**Header:** ``mockturtle/utils/tech_library.hpp``
+
+.. doc_overview_table:: classmockturtle_1_1exact__library
+ :column: Method
+
+ get_supergates
+ get_database
+ get_inverter_info
+
+.. doxygenclass:: mockturtle::exact_library
+ :members:
+
 Cuts
 ~~~~
 

experiments/mapper.cpp

@@ -47,7 +47,7 @@ std::string const mcnc_library = "GATE inv1 1 O=!a; PIN * INV 1 9
  "GATE inv3 3 O=!a; PIN * INV 3 999 1.1 0.09 1.1 0.09\n"
  "GATE inv4 4 O=!a; PIN * INV 4 999 1.2 0.07 1.2 0.07\n"
  "GATE nand2 2 O=!(ab); PIN * INV 1 999 1.0 0.2 1.0 0.2\n"
- "GATE nand3 3 O=!(abc);  PIN * INV 1 999 1.1 0.3 1.1 0.3\n"
+ "GATE nand3 3 O=!(abc); PIN * INV 1 999 1.1 0.3 1.1 0.3\n"
  "GATE nand4 4 O=!(abcd); PIN * INV 1 999 1.4 0.4 1.4 0.4\n"
  "GATE nor2 2 O=!{ab}; PIN * INV 1 999 1.4 0.5 1.4 0.5\n"
  "GATE nor3 3 O=!{abc}; PIN * INV 1 999 2.4 0.7 2.4 0.7\n"
@@ -91,7 +91,7 @@ int main()
  }
 
  tech_library_params tps;
- tech_library tech_lib( gates, tps );
+ tech_library<5, classification_type::np_configurations> tech_lib( gates, tps );
 
  for ( auto const& benchmark : epfl_benchmarks() )
  {
@@ -107,12 +107,13 @@ int main()
 
  map_params ps1;
  ps1.skip_delay_round = true;
- ps1.required_time = std::numeric_limits<float>::max();
+ ps1.required_time = std::numeric_limits<double>::max();
  map_stats st1;
 
  mig_network res1 = map( aig, exact_lib, ps1, &st1 );
 
  map_params ps2;
+ ps2.cut_enumeration_ps.minimize_truth_table = false;
  map_stats st2;
 
  klut_network res2 = map( aig, tech_lib, ps2, &st2 );

include/mockturtle/algorithms/cut_enumeration.hpp

@@ -641,7 +641,7 @@ template<typename Ntk, uint32_t NumVars, bool ComputeTruth, typename CutData>
 struct fast_network_cuts
 {
 public:
- static constexpr uint32_t max_cut_num = 26;
+ static constexpr uint32_t max_cut_num = 50;
  using cut_t = cut_type<ComputeTruth, CutData>;
  using cut_set_t = cut_set<cut_t, max_cut_num>;
  static constexpr bool compute_truth = ComputeTruth;

include/mockturtle/algorithms/cut_enumeration/exact_map_cut.hpp

@@ -43,10 +43,7 @@
 namespace mockturtle
 {
 
-/*! \brief Cut implementation based on ABC's giaMf.c
-
- See <a href="https://github.com/berkeley-abc/abc/blob/master/src/aig/gia/giaMf.c">giaMf.c</a> in ABC's repository.
-*/
+/*! \brief Cut implementation for graph mapping with a complete database */
 struct cut_enumeration_exact_map_cut
 {
  uint32_t delay{ 0 };

include/mockturtle/algorithms/cut_enumeration/tech_map_cut.hpp

@@ -43,6 +43,7 @@
 namespace mockturtle
 {
 
+/*! \brief Cut implementation for technology mapping */
 struct cut_enumeration_tech_map_cut
 {
  uint32_t delay{ 0 };