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Mirror of william_william/uvm-mcdf on Gitee

SystemVerilog 19 1 Updated Nov 30, 2022

one for all free music in china (origin edition)

Python 4,687 494 Updated Apr 1, 2024

Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare

278 96 Updated Mar 27, 2023

Simple AMBA VIP, Include axi/ahb/apb

SystemVerilog 15 Updated Jul 4, 2024

📺IPTV电视直播源更新项目『✨秒播级体验🚀』:支持IPv4/IPv6;支持自定义频道;支持本地源、组播源、酒店源、订阅源、关键字搜索;每天自动更新两次,结果可用于TVBox等播放软件;支持工作流、Docker(amd64/arm64/arm v7)、命令行、GUI运行方式 | IPTV live TV source update project

Python 11,741 2,970 Updated Jan 19, 2025

🗂️A file list/WebDAV program that supports multiple storages, powered by Gin and Solidjs. / 一个支持多存储的文件列表/WebDAV程序,使用 Gin 和 Solidjs。

Go 45,706 5,930 Updated Jan 18, 2025

Run macOS VM in a Docker! Run near native OSX-KVM in Docker! X11 Forwarding! CI/CD for OS X Security Research! Docker mac Containers.

Shell 49,343 2,764 Updated Nov 18, 2024

VIP for AXI Protocol

SystemVerilog 120 36 Updated May 24, 2022

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

SystemVerilog 108 51 Updated Nov 29, 2017

AMBA AXI VIP

SystemVerilog 370 106 Updated Jun 28, 2024

整理各大佬的阅读书源合集(自用)

171 10 Updated Sep 27, 2024

洛雪音乐音源、MusicFree音源、落雪音乐音源

JavaScript 2,784 181 Updated Jan 16, 2025

The UVM written in Python

Python 393 76 Updated Jan 11, 2025

Novel GUI Based UVM Testbench Template Builder

Python 123 46 Updated Apr 14, 2021

Generation of diagrams like flowcharts or sequence diagrams from text in a similar manner as markdown

TypeScript 74,537 6,823 Updated Jan 19, 2025
SystemVerilog 4 1 Updated Aug 21, 2021

用 Vue3 和 Go 搭建的微软 New Bing 演示站点,拥有一致的 UI 体验,支持 ChatGPT 提示词,国内可用。

HTML 8,821 13,265 Updated Mar 20, 2024

uvm AXI BFM(bus functional model)

Verilog 236 113 Updated Jun 23, 2013

Reference examples and short projects using UVM Methodology

SystemVerilog 254 154 Updated May 18, 2022
SystemVerilog 5 3 Updated Jun 5, 2017

AXI 总线验证 模块

SystemVerilog 8 3 Updated Feb 9, 2020

SoC Based on ARM Cortex-M3

Verilog 25 10 Updated Jan 16, 2025

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,181 273 Updated Jan 16, 2025

AXI总线连接器

SystemVerilog 93 22 Updated Mar 26, 2020