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Merge branch 'master' of git://git.denx.de/u-boot-video
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* 'master' of git://git.denx.de/u-boot-video:
  video: atmel/lcd: add LCD driver for new Atmel SoC
  video: cfb_console: flush dcache for frame buffer in DRAM
  cfb_console: Ignore bell character
  cfb_console: Add console_clear_line function
  cfb_console: Fix function console_back
  omap3_dss: cosmetic changes
  omap3_dss: add optional framebuffer
  mx53loco: Add LCD support
  mx5: Rename mx51_fb_init()
  mx53: Allow IPUv3 driver to also work on mx53
  mx51evk: Add LCD support
  EXYNOS: display 32bpp bitmap TIZEN logo
  create lib/tizen directory
  LCD: display 32bpp decompressed bitmap image
  common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef
  common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs
  common/lcd.c: use ARRAY_SIZE
  cmd_bmp.c: make bmp_display() usable by drivers or board code
  LCD: support another s6e8ax0 panel type
  LCD: change s6e8ax0 panel gamma value
  include/video.h: drop unused video_printf()

Signed-off-by: Wolfgang Denk <[email protected]>
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@wdenx
wdenx committed Jun 7, 2012
2 parents 74b5b5d + f6b690e commit fedab33
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Showing 32 changed files with 6,123 additions and 122 deletions.
3 changes: 3 additions & 0 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -229,6 +229,9 @@ LIBS = lib/libgeneric.o
LIBS += lib/lzma/liblzma.o
LIBS += lib/lzo/liblzo.o
LIBS += lib/zlib/libz.o
ifeq ($(CONFIG_TIZEN),y)
LIBS += lib/tizen/libtizen.o
endif
LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
"board/$(VENDOR)/common/lib$(VENDOR).o"; fi)
LIBS += $(CPUDIR)/lib$(CPU).o
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1 change: 1 addition & 0 deletions arch/arm/include/asm/arch-exynos/mipi_dsim.h
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Expand Up @@ -329,6 +329,7 @@ struct mipi_dsim_lcd_device {
char *name;
int id;
int bus_id;
int reverse_panel;

struct mipi_dsim_device *master;
void *platform_data;
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8 changes: 6 additions & 2 deletions arch/arm/include/asm/arch-mx5/imx-regs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,8 @@

#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_CTRL_BASE_ADDR 0x40000000
#define IPU_SOC_BASE_ADDR 0x40000000
#define IPU_SOC_OFFSET 0x1E000000
#define SPBA0_BASE_ADDR 0x70000000
#define AIPS1_BASE_ADDR 0x73F00000
#define AIPS2_BASE_ADDR 0x83F00000
Expand All @@ -34,7 +35,8 @@
#define NFC_BASE_ADDR_AXI 0xCFFF0000
#define CS1_BASE_ADDR 0xB8000000
#elif defined(CONFIG_MX53)
#define IPU_CTRL_BASE_ADDR 0x18000000
#define IPU_SOC_BASE_ADDR 0x18000000
#define IPU_SOC_OFFSET 0x06000000
#define SPBA0_BASE_ADDR 0x50000000
#define AIPS1_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR 0x63F00000
Expand All @@ -48,6 +50,8 @@
#error "CPU_TYPE not defined"
#endif

#define IPU_CTRL_BASE_ADDR IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET

#define IRAM_SIZE 0x00020000 /* 128 KB */

/*
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61 changes: 39 additions & 22 deletions arch/arm/include/asm/arch-omap3/dss.h
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Expand Up @@ -28,22 +28,33 @@
#ifndef DSS_H
#define DSS_H

/*
* DSS Base Registers
*/
#define OMAP3_DSS_BASE 0x48050040
#define OMAP3_DISPC_BASE 0x48050440
/* DSS Base Registers */
#define OMAP3_DSS_BASE 0x48050000
#define OMAP3_DISPC_BASE 0x48050400
#define OMAP3_VENC_BASE 0x48050C00

/* DSS Registers */
struct dss_regs {
u32 revision; /* 0x00 */
u8 res1[12]; /* 0x04 */
u32 sysconfig; /* 0x10 */
u32 sysstatus; /* 0x14 */
u32 irqstatus; /* 0x18 */
u8 res2[36]; /* 0x1C */
u32 control; /* 0x40 */
u32 sdi_control; /* 0x44 */
u32 pll_control; /* 0x48 */
};

/* DISPC Registers */
struct dispc_regs {
u32 revision; /* 0x00 */
u8 res1[12]; /* 0x04 */
u32 sysconfig; /* 0x10 */
u32 sysstatus; /* 0x14 */
u32 irqstatus; /* 0x18 */
u32 irqenable; /* 0x1C */
u8 res2[32]; /* 0x20 */
u32 control; /* 0x40 */
u32 config; /* 0x44 */
u32 reserve_2; /* 0x48 */
Expand All @@ -60,6 +71,18 @@ struct dispc_regs {
u32 global_alpha; /* 0x74 */
u32 size_dig; /* 0x78 */
u32 size_lcd; /* 0x7C */
u32 gfx_ba0; /* 0x80 */
u32 gfx_ba1; /* 0x84 */
u32 gfx_position; /* 0x88 */
u32 gfx_size; /* 0x8C */
u8 unused[16]; /* 0x90 */
u32 gfx_attributes; /* 0xA0 */
u32 gfx_fifo_threshold; /* 0xA4 */
u32 gfx_fifo_size_status; /* 0xA8 */
u32 gfx_row_inc; /* 0xAC */
u32 gfx_pixel_inc; /* 0xB0 */
u32 gfx_window_skip; /* 0xB4 */
u32 gfx_table_ba; /* 0xB8 */
};

/* VENC Registers */
Expand Down Expand Up @@ -123,6 +146,13 @@ struct venc_regs {
#define TFTSTN_SHIFT 3
#define DATALINES_SHIFT 8

#define GFX_ENABLE 1
#define GFX_FORMAT_SHIFT 1
#define LOADMODE_SHIFT 1

#define DSS_SOFTRESET (1 << 1)
#define DSS_RESETDONE 1

/* Enabling Display controller */
#define LCD_ENABLE 1
#define DIG_ENABLE (1 << 1)
Expand All @@ -131,26 +161,14 @@ struct venc_regs {
#define GP_OUT0 (1 << 15)
#define GP_OUT1 (1 << 16)

#define DISPC_ENABLE (LCD_ENABLE | \
DIG_ENABLE | \
GO_LCD | \
GO_DIG | \
GP_OUT0| \
GP_OUT1)

/* Configure VENC DSS Params */
#define VENC_CLK_ENABLE (1 << 3)
#define DAC_DEMEN (1 << 4)
#define DAC_POWERDN (1 << 5)
#define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16
#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
DAC_DEMEN | \
DAC_POWERDN | \
VENC_OUT_SEL)
/*
* Panel Configuration
*/

/* Panel Configuration */
struct panel_config {
u32 timing_h;
u32 timing_v;
Expand All @@ -161,11 +179,10 @@ struct panel_config {
u32 data_lines;
u32 load_mode;
u32 panel_color;
void *frame_buffer;
};

/*
* Generic DSS Functions
*/
/* Generic DSS Functions */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width);
void omap3_dss_panel_config(const struct panel_config *panel_cfg);
Expand Down
59 changes: 59 additions & 0 deletions board/freescale/mx51evk/mx51evk.c
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Expand Up @@ -36,6 +36,12 @@
#include <fsl_pmic.h>
#include <mc13892.h>
#include <usb/ehci-fsl.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>

#define MX51EVK_LCD_3V3 (3 * 32 + 9) /* GPIO4_9 */
#define MX51EVK_LCD_5V (3 * 32 + 10) /* GPIO4_10 */
#define MX51EVK_LCD_BACKLIGHT (2 * 32 + 4) /* GPIO3_4 */

DECLARE_GLOBAL_DATA_PTR;

Expand Down Expand Up @@ -453,13 +459,62 @@ int board_mmc_init(bd_t *bis)
}
#endif

static struct fb_videomode claa_wvga = {
.name = "CLAA07LC0ACW",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 37037,
.left_margin = 40,
.right_margin = 60,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};

void lcd_iomux(void)
{
/* DI2_PIN15 */
mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);

/* Pad settings for MX51_PIN_DI2_DISP_CLK */
mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);

/* Turn on 3.3V voltage for LCD */
mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
gpio_direction_output(MX51EVK_LCD_3V3, 1);

/* Turn on 5V voltage for LCD */
mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
gpio_direction_output(MX51EVK_LCD_5V, 1);

/* Turn on GPIO backlight */
mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
INPUT_CTL_PATH1);
gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
}

void lcd_enable(void)
{
int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565);
if (ret)
printf("LCD cannot be configured: %d\n", ret);
}

int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
#ifdef CONFIG_USB_EHCI_MX5
setup_usb_h1();
#endif
lcd_iomux();

return 0;
}
Expand All @@ -469,6 +524,8 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

lcd_enable();

return 0;
}

Expand All @@ -479,6 +536,8 @@ int board_late_init(void)
setup_iomux_spi();
power_init();
#endif
setenv("stdout", "serial");

return 0;
}
#endif
Expand Down
72 changes: 72 additions & 0 deletions board/freescale/mx53loco/mx53loco.c
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Expand Up @@ -39,6 +39,10 @@
#include <pmic.h>
#include <dialog_pmic.h>
#include <fsl_pmic.h>
#include <linux/fb.h>
#include <ipu_pixfmt.h>

#define MX53LOCO_LCD_POWER (2 * 32 + 24) /* GPIO3_24 */

DECLARE_GLOBAL_DATA_PTR;

Expand Down Expand Up @@ -402,10 +406,74 @@ static void clock_1GHz(void)
printf("CPU: Switch DDR clock to 400MHz failed\n");
}

static struct fb_videomode claa_wvga = {
.name = "CLAA07LC0ACW",
.refresh = 57,
.xres = 800,
.yres = 480,
.pixclock = 37037,
.left_margin = 40,
.right_margin = 60,
.upper_margin = 10,
.lower_margin = 10,
.hsync_len = 20,
.vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};

void lcd_iomux(void)
{
mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0);

/* Turn on GPIO backlight */
mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1);
gpio_direction_output(MX53LOCO_LCD_POWER, 1);

/* Turn on display contrast */
mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1);
}

void lcd_enable(void)
{
int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565);
if (ret)
printf("LCD cannot be configured: %d\n", ret);
}

int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_fec();
lcd_iomux();

return 0;
}
Expand All @@ -432,6 +500,8 @@ int board_late_init(void)
clock_1GHz();
print_cpuinfo();

setenv("stdout", "serial");

return 0;
}
#endif
Expand All @@ -442,6 +512,8 @@ int board_init(void)

mxc_set_sata_internal_clock();

lcd_enable();

return 0;
}

Expand Down
16 changes: 16 additions & 0 deletions board/samsung/trats/trats.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@
#include <pmic.h>
#include <usb/s3c_udc.h>
#include <max8997_pmic.h>
#include <libtizen.h>

#include "setup.h"

Expand All @@ -53,6 +54,11 @@ u32 get_board_rev(void)

static void check_hw_revision(void);

static int hwrevision(int rev)
{
return (board_rev & 0xf) == rev;
}

int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
Expand Down Expand Up @@ -491,6 +497,16 @@ void init_panel_info(vidinfo_t *vid)
vid->reset_delay = 0;
vid->interface_mode = FIMD_RGB_INTERFACE;
vid->mipi_enabled = 1;
vid->logo_on = 1,
vid->resolution = HD_RESOLUTION,
vid->rgb_mode = MODE_RGB_P,

#ifdef CONFIG_TIZEN
get_tizen_logo_info(vid);
#endif

if (hwrevision(2))
mipi_lcd_device.reverse_panel = 1;

strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name);
s6e8ax0_platform_data.lcd_power = lcd_power;
Expand Down
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