fix(spi): Fix bus clock for ESP32-P4 + remove S2 leftover #11547
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P-R-O-C-H-Y
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Area: Peripherals API
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Test Results 76 files 76 suites 13m 6s ⏱️ Results for commit 13333d2. ♻️ This comment has been updated with latest results. |
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Pull Request Overview
This PR updates SPI initialization for the ESP32-P4 target by adding proper low-level SPI clock handling and removing outdated S2 support.
- Adds
hal/spi_ll.hinclude for ESP32-P4 - Removes legacy DPORT-based clock/reset for unsupported configurations
- Implements atomic clock enable/reset for FSPI and HSPI on ESP32-P4
Comments suppressed due to low confidence (2)
cores/esp32/esp32-hal-spi.c:663
- [nitpick] Consider adding a brief comment explaining the purpose of this ESP32-P4–specific atomic clock/reset block to clarify why legacy DPORT calls were removed.
#elif CONFIG_IDF_TARGET_ESP32P4
cores/esp32/esp32-hal-spi.c:664
- This new ESP32-P4 path introduces logic for both FSPI and HSPI; consider adding unit or integration tests covering both branches to prevent regressions on P4.
if (spi_num == FSPI) {
me-no-dev
approved these changes
Jul 3, 2025
me-no-dev
added
Status: Pending Merge
Memory usage test (comparing PR against master branch)The table below shows the summary of memory usage change (decrease - increase) in bytes and percentage for each target.
Click to expand the detailed deltas report [usage change in BYTES]
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Description of Change
This pull request updates the SPI handling for the ESP32P4 target in the
cores/esp32/esp32-hal-spi.cfile. It introduces new logic for enabling and resetting SPI bus clocks specific to ESP32P4 and removes legacy handling for unsupported configurations.Tests scenarios
Tested using ESP32-P4 and SD card example. Tested both FSPI and HSPI.
Related links
Closes #11398