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High quality and composable RTL libraries in SystemVerilog
Fixed point math library for SystemVerilog
Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
An attempt to recreate the RP2040 PIO in an FPGA
Communication framework for RTL simulation and emulation.
Minimax: a Compressed-First, Microcoded RISC-V CPU
IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.
Recommended C code style and coding rules for standard C99 or later
An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。
Python and tab completion, better together.
MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
HDL code for a complex multiplier with AXI stream Interface
xk265：HEVC/H.265 Video Encoder IP Core (RTL)
c common functions library extracted from my open source project FastDFS. this library is very simple and stable. functions including: string, logger, chain, hash, socket, ini file reader, base64 e…
🎨 A curated list of delightful VS Code packages and resources.