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Merge tag 'pinctrl-v4.18-3' of git://git.kernel.org/pub/scm/linux/ker…
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…nel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

 - A slew of driver fixes for Mediatek mt7622

 - Fix a direction inversion bug in the Ingenic driver

 - Fix unsupported drive strength setting on the PFC r8a77970

 - Off by one and NULL dereference fixes in the NSP driver

* tag 'pinctrl-v4.18-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: nsp: Fix potential NULL dereference
  pinctrl: nsp: off by ones in nsp_pinmux_enable()
  pinctrl: sh-pfc: r8a77970: remove SH_PFC_PIN_CFG_DRIVE_STRENGTH flag
  pinctrl: ingenic: Fix inverted direction for < JZ4770
  pinctrl: mt7622: fix a kernel panic when gpio-hog is being applied
  pinctrl: mt7622: stop using the deprecated pinctrl_add_gpio_range
  pinctrl: mt7622: fix that pinctrl_claim_hogs cannot work
  pinctrl: mt7622: fix initialization sequence between eint and gpiochip
  pinctrl: mt7622: fix error path on failing at groups building
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torvalds committed Jul 16, 2018
2 parents 706bf68 + c29e9da commit 30b06ab
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Showing 4 changed files with 44 additions and 26 deletions.
6 changes: 4 additions & 2 deletions drivers/pinctrl/bcm/pinctrl-nsp-mux.c
Original file line number Diff line number Diff line change
Expand Up @@ -460,8 +460,8 @@ static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
const struct nsp_pin_function *func;
const struct nsp_pin_group *grp;

if (grp_select > pinctrl->num_groups ||
func_select > pinctrl->num_functions)
if (grp_select >= pinctrl->num_groups ||
func_select >= pinctrl->num_functions)
return -EINVAL;

func = &pinctrl->functions[func_select];
Expand Down Expand Up @@ -577,6 +577,8 @@ static int nsp_pinmux_probe(struct platform_device *pdev)
return PTR_ERR(pinctrl->base0);

res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res)
return -EINVAL;
pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start,
resource_size(res));
if (!pinctrl->base1) {
Expand Down
48 changes: 33 additions & 15 deletions drivers/pinctrl/mediatek/pinctrl-mt7622.c
Original file line number Diff line number Diff line change
Expand Up @@ -1424,7 +1424,7 @@ static struct pinctrl_desc mtk_desc = {

static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
int value, err;

err = mtk_hw_get_value(hw, gpio, PINCTRL_PIN_REG_DI, &value);
Expand All @@ -1436,7 +1436,7 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)

static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct mtk_pinctrl *hw = dev_get_drvdata(chip->parent);
struct mtk_pinctrl *hw = gpiochip_get_data(chip);

mtk_hw_set_value(hw, gpio, PINCTRL_PIN_REG_DO, !!value);
}
Expand Down Expand Up @@ -1508,11 +1508,20 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
if (ret < 0)
return ret;

ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
chip->ngpio);
if (ret < 0) {
gpiochip_remove(chip);
return ret;
/* Just for backward compatible for these old pinctrl nodes without
* "gpio-ranges" property. Otherwise, called directly from a
* DeviceTree-supported pinctrl driver is DEPRECATED.
* Please see Section 2.1 of
* Documentation/devicetree/bindings/gpio/gpio.txt on how to
* bind pinctrl and gpio drivers via the "gpio-ranges" property.
*/
if (!of_find_property(np, "gpio-ranges", NULL)) {
ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
chip->ngpio);
if (ret < 0) {
gpiochip_remove(chip);
return ret;
}
}

return 0;
Expand Down Expand Up @@ -1695,15 +1704,16 @@ static int mtk_pinctrl_probe(struct platform_device *pdev)
mtk_desc.custom_conf_items = mtk_conf_items;
#endif

hw->pctrl = devm_pinctrl_register(&pdev->dev, &mtk_desc, hw);
if (IS_ERR(hw->pctrl))
return PTR_ERR(hw->pctrl);
err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
&hw->pctrl);
if (err)
return err;

/* Setup groups descriptions per SoC types */
err = mtk_build_groups(hw);
if (err) {
dev_err(&pdev->dev, "Failed to build groups\n");
return 0;
return err;
}

/* Setup functions descriptions per SoC types */
Expand All @@ -1713,17 +1723,25 @@ static int mtk_pinctrl_probe(struct platform_device *pdev)
return err;
}

err = mtk_build_gpiochip(hw, pdev->dev.of_node);
if (err) {
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
/* For able to make pinctrl_claim_hogs, we must not enable pinctrl
* until all groups and functions are being added one.
*/
err = pinctrl_enable(hw->pctrl);
if (err)
return err;
}

err = mtk_build_eint(hw, pdev);
if (err)
dev_warn(&pdev->dev,
"Failed to add EINT, but pinctrl still can work\n");

/* Build gpiochip should be after pinctrl_enable is done */
err = mtk_build_gpiochip(hw, pdev->dev.of_node);
if (err) {
dev_err(&pdev->dev, "Failed to add gpio_chip\n");
return err;
}

platform_set_drvdata(pdev, hw);

return 0;
Expand Down
2 changes: 1 addition & 1 deletion drivers/pinctrl/pinctrl-ingenic.c
Original file line number Diff line number Diff line change
Expand Up @@ -536,7 +536,7 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
} else {
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, input);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
}

Expand Down
14 changes: 6 additions & 8 deletions drivers/pinctrl/sh-pfc/pfc-r8a77970.c
Original file line number Diff line number Diff line change
Expand Up @@ -21,15 +21,13 @@
#include "core.h"
#include "sh_pfc.h"

#define CFG_FLAGS SH_PFC_PIN_CFG_DRIVE_STRENGTH

#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_CFG_22(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_6(4, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(5, fn, sfx, CFG_FLAGS)
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_28(1, fn, sfx), \
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_6(4, fn, sfx), \
PORT_GP_15(5, fn, sfx)
/*
* F_() : just information
* FM() : macro for FN_xxx / xxx_MARK
Expand Down

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