Hardware-Based Acceleration of Matrix MAC on an FPGA
This project aims to develop a hardware-based acceleration solution for matrix multiply-accumulate (MAC) operations. We are designing a RISC-V-based processor with a custom instruction set architecture (ISA) optimized for efficient matrix MAC computations. By incorporating dedicated hardware accelerators and advanced optimization techniques, our goal is to enhance the performance and power efficiency of matrix operations, particularly in the context of machine learning and scientific computing applications.
| Book Title | Author | Book Link | Video Lectures |
|---|---|---|---|
| (The Morgan Kaufmann Series in Computer Architecture and Design) - Computer Organization and Design RISC-V Edition. | David A. Patterson, John L. Hennessy | Link 1 | Link 1 |
| Digital Design and Computer Architecture, Second Edition (2012, Morgan Kaufmann). | David Harris, Sarah Harris - | Link 1 | None Found Yet |
Although the exact edition doesn't matter, just use the latest as possible.
| Name | Purpose | Description | Link |
|---|---|---|---|
| Xilinx Vivado | Writing Veriloge | To write and simulate the whole code, The Main Software of our whole Project. important!! Install while keeping the internet off, and install the Design suite. | Link 1 |
| RISC-V Online Simulator | RISC-V Simulation | Use it to write RISC_V Assembly code and easly convert it to hex and test it alongside our/your processor | link 1 |
| DigitalUS Online | Generating Schematics | To generate and simulate Schematics for modules online through Verilog code directly | link 1 |
| Source Name | Description | Link |
|---|---|---|
| Verilog in 2 Hours | Understanding of Verilog, How to Write it and How to Use It | Link 1 |
| RISC-V Single Cycle Core Implementation | Verilog implementation of MERL Architecture, in ENGLISH & Urdu, Quiete good for understanding modules Like ALU, CU, etc | Link 2 |
| RISC-V Pipeline Implementation | MERL Architecture Pipeline Implementation In Urdu & English | Link 3 |
| RISC-V Online Course | A complete and perfect course for understanding the RISC-V architecture and its implementation. week-3 to week-10 preferred. | link 4 |
| Introduction to FPGA | Understand of FPGA and Verilog and how to use them together. | Link 5 |
| RISC-V Core | A 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM. | Link 6 |
| RISC-V Pipelined Core | Pipeline version of the above core. | Link 7 |
| RISC-V Matrix Extension Specification | This is a matrix extension proposal for AI applications under RISC-V architecture. The extension has the following features. | Link 8 |
| Tiny Matrix Extension using RISC-V Custom Instructions | a processor that accelerates matrix multiplication using RISC-V custom instructions, implements it on an FPGA board and evaluates its performance. | Link 9 |
| Objectives | Date Started | Date Completed | Achived? | Version | Test's |
|---|---|---|---|---|---|
| Single Cycle Processor | 1/July/2023 | 27/July/2023 | True | 1.2 | Test-1 |
| 5 stages Pipelined Processor | 30/July/2023 | 29/Aug/2023 | True | 2.0 | Test-2 |
| Convert the Whole Project into System Verloge | Pending... | pending... | False | 0.0 | |
| MAC Instructions | Pending... | pending... | False | 0.0 | |
| FPGA Implementation | Pending... | pending... | False | 0.0 |
| FETCH_CYCLE | DECODE_CYCLE | EXECUTE_CYCLE | MEMORY_CYCLE | WRITEBACK_CYCLE |
|---|---|---|---|---|
| PC Mux | Control Unit | AND GATE | Data Memory | MUX |
| Program Counter | Register File | MUX | Memory Stage Registers | - |
| Adder | Extender | PC ADDER | - | - |
| Instruction Memory | Deocde Stage Registers | ALU | - | - |
| - | - | Execute Stage Registers | - | - |
This project is licensed under MIT license.
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