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Commits on Jul 21, 2022

• repeater: fix bug that drop reqs by last unenq reqs (OpenXiangShan#1672)

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• l1tlb: add ptw resp bypass logic & re-add multi-hit assert check (OpenXiangShan#1665)

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Commits on Jul 19, 2022

• l2tlb.cache: fix bug that read valid&data at different stage (OpenXiangShan#1663)

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Commits on Jul 18, 2022

• dtlb: change volume from s128f8 to s64f16 (OpenXiangShan#1662)

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• l1tlb: tlb's req port can be configured to be block or non-blocked (OpenXiangShan#1656)

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Commits on Jul 14, 2022

• dtlb: merge duplicated tlb together: one ld-tlb and one st-tlb. (OpenXiangShan#1654)

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• l1tlb: l1tlb entry uses one-hot size for timing optimization (OpenXiangShan#1626)

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Commits on Jul 9, 2022

• dtlb: replace sram with SyncDataModule (OpenXiangShan#1627)

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Commits on Jun 26, 2022

• l2tlb: add counter to ptw-filter to avoid l2tlb deadlock & sync sfence to mmu (OpenXiangShan#1599)

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Commits on Jun 25, 2022

• l2tlb: delay one cycle when read from sram (OpenXiangShan#1596)

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• tlb: divide v-select into two cycle for timing optimization (OpenXiangShan#1598)

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Commits on Jun 6, 2022

• util.sram: rm a r/w hazard mux which is not needed. bump huancun (OpenXiangShan#1571)

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Commits on May 21, 2022

• bump difftest, add vcs param for dump-wave and diff (OpenXiangShan#1557)

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Commits on Apr 14, 2022

• mmu.l2tlb: divide missqueue into 'missqueue' and llptw (OpenXiangShan#1522)

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Commits on Apr 1, 2022

• l2tlb.cache: store invalid entries(only super entries) into sp to avoid mem access waste (OpenXiangShan#1518)

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Commits on Mar 30, 2022

• sram-tlb: change SRAMTemplate & when tlb refill, just resp a miss/fast_miss (OpenXiangShan#1504)

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Commits on Feb 1, 2022

• l2tlb: req from missqueue doesn't cause prefetch (OpenXiangShan#1448)

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Commits on Jan 23, 2022

• pmp: fix bug of l locks cfg's modification (OpenXiangShan#1438)

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Commits on Dec 29, 2021

• csr: add one/two cycle for signals customCtrl/tlb/csrUpdate (OpenXiangShan#1405)

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Commits on Dec 26, 2021

• atomic: add static pmp relative modification (OpenXiangShan#1394)

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Commits on Dec 21, 2021

• bump ready-to-run, update nemu so for xtvec vector mode (OpenXiangShan#1381)

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Commits on Dec 17, 2021

• pmp: add static pmp check that stored in tlb entries (OpenXiangShan#1366)

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Commits on Dec 15, 2021

• mmpma: fix mmpma's read/write decoupled logic (OpenXiangShan#1354)

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Commits on Dec 11, 2021

• mmu: timing optimization of ptwfilter's recv and issue & storeunit's mmio (OpenXiangShan#1326)

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Commits on Dec 8, 2021

• csr: add write mask to satp.ppn & xstatus.xs (OpenXiangShan#1323)

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Commits on Dec 6, 2021

• Updated to priv 1.12 (OpenXiangShan#1301)

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Commits on Dec 1, 2021

• mmu: timing optimization for TLB's mux, PTWFilter and LoadUnit's fastUop (OpenXiangShan#1270)

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Commits on Nov 12, 2021

• Merge remote-tracking branch 'origin/master' into dtlb-pipe

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• l2tlb.cache: fix bug of PipelineConnect's usage, add InsideStageConnect

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• l2tlb: fix bug of page cahce's resp.ready

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• l2tlb: add Non-blocking PTWRepeater[NB] connecting PtwFilter

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Commits on Nov 11, 2021

• l2tlb.fsm: fix bug, when af, state wrongly changes

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• tlb: timing optimization in 'genPPN', 'pmp check' and 'data out when nWays is 1' (OpenXiangShan#1210)

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Commits on Nov 5, 2021

• pma: update pma init config (OpenXiangShan#1200)

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Commits on Nov 2, 2021

• pmp: timing optimization, from mux chain to ParallelPriorityMux (OpenXiangShan#1193)

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