Awesome SpinalHDL

This is a curated list of SpinalHDL projects, libraries, and learning resources.

Feel free to open a merge request if you would like to see anything added.

Learning Resources

• SpinalHDL Documentation
• Spinal-bootcamp - Tutorial based on Jupyter Notebook
• SpinalHDL labs - Labs to learn SpinalHDL

CPU

• VexRiscV - A FPGA friendly 32 bit RISC-V CPU implementation
• VexiiRiscv - Successor to VexRiscV
• NaxRiscv - Superscalar RISC-V core
• J1Sc - A reimplementation of a tiny stack CPU
• NOP-Core - High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
• FPGACosmacELF - A re-creation of a Cosmac ELF computer
• Proteus - The SpinalHDL design of the Proteus core, an extensible RISC-V core.
• flare32_cpu - 32-bit CPU
• shdl6800 - 6800 processor
• MIPS CPU - MIPS with 5-stage pipeline
• OPCSH - One Page CPU
• Subleq Spinalhdl - Subleq CPU
• MicroRV32 - FPGA Suitable RTL Implementation of RISC-V RV32
• mr1 - Formally verified RISC-V CPU
• LAS32 - Loongarch 32-bits Reduced ISA CPU
• eepyu - 4-stage pipelined RISC-V CPU

SoC

• SaxonSoc - SoC based on VexRiscv and ICE40 UP5K

Neural Network Accelerators

• SpinalHDL_CNN_Accelerator - CNN accelerator implemented with Spinal HDL
• SpAtten - [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
• SpinalResNet - AdderNet ResNet20 for cifar10

I/O

• FPGA-PWM Module - A FPGA-based PWM module with support for I2C and SPI

Memory

• Clio - Disaggregated memory system that virtualizes, protects, and manages disaggregated memory at hardware-based memory nodes
• FPGA Multiport RAMs - FPGA friendly Multiport memories (N-read-M-write) based on LVT

Math

• math - SpinalHDL Hardware Floating Point Math Library
• fpu-wrappers - Wrappers for open source FPU hardware implementations.
• SpinalHDL Integer Divider - Integer division module
• PiMAC - Pipelined multiplier

Cryptography

• SpinalCrypto - Cryptography library
• Poseidon-SpinalHDL - Implementation of Poseidon hash function
• xoroshiro - xoroshiro32++ and xoroshiro64++ PRNG algorithms

Networking

• SpinalCorundum - Components for Corundum Ethernet
• BlackwireSpinal - Components implementing WireGuard primitives for Corundum Ethernet
• Programmed I/O (PIO) NIC on Enzian - Network interface card with PCI-E for Enzian platform

Signal Processing

• SpinalFFT - A FFT hardware generator in SpinalHDL
• FFT_Radix_6 - FFT Radix-6 design
• Chainsaw - A hardware design library for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communication and Crypto applications

Audio

• spinal_synth - Simple synth

Graphics

• rt - A Full Hardware Real-Time Ray-Tracer