fayzanx
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RISCV-32BitCPU Public
A verilog (FPGA based) project & Logisim simulation for creating a functional RISC-V 32-bit CPU running all instructions.
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FPGA-VerilogHDL-Course Public
Some Examples and their solutions in VerilogHDL targeted to DE1 FPGA board.
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chess-gui-multiplayer Public
A simple multiplayer GUI chess game in C++
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Book-Store-Management-System Public
Forked from Armour/Book-Store-Management-SystemA simple but useful C++ program, assignment 1 in OOP course