A Python library for writing VHDL 2008 code. It's necessary to know both languages to use this.
It's inspired by the Amaranth HDL.
-
Notifications
You must be signed in to change notification settings - Fork 0
A Python library for writing SystemVerilog code with a DSL.
License
fl4shk/pyhdlgen
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
A Python library for writing SystemVerilog code with a DSL.
Resources
License
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published