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Add hardcoded flint_mpn_aors_n for ARM and x86 #2118

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Add hardcoded flint_mpn_aors_n for ARM and x86 #2118

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d09c98e
Add hardcoded flint_mpn_aors_n for ARM and x86
Nov 27, 2024
00ecdcb
Start on aorsrsh for x86
Nov 30, 2024
9ce9168
Add generation for hardcoded flint_mpn_addrsh
Dec 2, 2024
c806930
Also subrsh
Dec 2, 2024
62a6c20
Fixup
Dec 2, 2024
e63d4f7
fixup
Dec 2, 2024
2daf43a
Add corresponding C sources for aorsrsh
Dec 2, 2024
96786cd
Add tests for aorsrsh
Dec 2, 2024
65fadb4
blabla
Dec 2, 2024
877ec63
bla
Dec 2, 2024
a537b89
fixup
Dec 2, 2024
55dd138
fixup
Dec 2, 2024
9e7f462
Stash for aorsrsh for ARM64
Dec 9, 2024
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fixup
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Albin Ahlbäck committed Dec 2, 2024
commit e63d4f7e7445335a00b03fe086d94d0853ce81a8
5 changes: 2 additions & 3 deletions src/mpn_extras/x86_64/broadwell/aorsrsh_hard.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -53,11 +53,10 @@ dnl u -= s C sbb
dnl rp[i] = u C mov
dnl fi

dnl Non-optimized. We probably should optimize add and sub differently. We
dnl probably need to use more registers to interleave more.
dnl Non-optimized version.
ifdef(blablablabla,`
ALIGN(16)
PROLOGUE(flint_mpn_addrsh_5)
PROLOGUE(flint_mpn_aorsrsh_5)
xor R32(tnc), R32(tnc)
sub cnt, tnc
xor R32(sx), R32(sx)
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