OpenTitan Demonstrators

Tools for embedded/bare-metal development using bazel

64-bit multicore Linux-capable RISC-V processor

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

OpenTitan: Open source silicon root of trust

Adding support for LEON3 - LEON5 - NOELV on terasic DE10 nano and DE0 nano boards

Add support for PS/2 & VGA on leon3, based on rtems 4.10

Gaisler Leon3 processor on the Digilent Genesys FPGA.

A test of a leon 3 processor

Example TASTE project for LEON3 with direct driver calls and external libraries

This repository contains the design of the ASIST Leon3 processor with AES support

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

Learning FPGA, yosys, nextpnr, and RISC-V

A huge VHDL library for FPGA development

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

A Python toolbox for building complex digital hardware

4 channel 1GS/s DDS (AD9910 or AD9912 variant)

Ground station connection/data management software

VNx: Vitis Network Examples

This repo contains the Limago code

OBC hardware for UPSat

OBC software for UPSat

上位机软件 这里主要完成算法的处理和界面的显示和控制。 关于算法部分需要后面补充，目前没有完全消化。 处理流程： 1. 初始化USB，然后上位机通过控制端点发送写命令控制字（不加帧头命令）下位机未处理，开启监视工作线程循环，主要内容是：通过控制端点发送读命令控制字，通过控制端点读回串口信息，用来验证设备是否启动握手成功（0X55）。 2. 启动成功后引发响应的启动触发方法。启动触发方法中，先…

本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取固件的信息状态描述后，通过上电复位或者手动复位，通过串口发送0X55给上位机，表明链路打通，一次握手成功。 2. 超声波发射与AD数据接收：在收到上位机通…

Marvell/Aquantia AQC111u MultiGigabit 2.5GbE/5GbE USB3 NIC Driver for XCP-ng

Source and Hardware file of PE1005S camera Module interfacing with Cypress FX3 USB 3.0

FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD