Several I/O-related updates (lsils#506)

* update lorina

* update test

* update verilog io

* buffered network names

* update bill

* missing include

include/mockturtle/io/verilog_reader.hpp

@@ -118,6 +118,10 @@ class verilog_reader : public lorina::verilog_reader
  {
  signals_[name] = ntk_.create_pi( name );
  input_names_.emplace_back( name, 1u );
+ if constexpr ( has_set_name_v<Ntk> )
+ {
+ ntk_.set_name( signals_[name], name );
+ }
  }
  else
  {
@@ -128,6 +132,10 @@ class verilog_reader : public lorina::verilog_reader
  const auto sname = fmt::format( "{}[{}]", name, i );
  word.push_back( ntk_.create_pi( sname ) );
  signals_[sname] = word.back();
+ if constexpr ( has_set_name_v<Ntk> )
+ {
+ ntk_.set_name( signals_[sname], sname );
+ }
  }
  registers_[name] = word;
  input_names_.emplace_back( name, length );
@@ -350,35 +358,37 @@ class verilog_reader : public lorina::verilog_reader
 
  add_register( args[2].second, montgomery_multiplication( ntk_, registers_[args[0].second], registers_[args[1].second], N, NN ) );
  }
- else
+ else if ( module_name == "buffer" || module_name == "inverter" )
  {
  if constexpr( is_buffered_network_type_v<Ntk> )
  {
  static_assert( has_create_buf_v<Ntk>, "Ntk does not implement the create_buf method" );
-
- if ( module_name == "buffer" || module_name == "inverter" )
+ if ( !num_args_equals( 2u ) )
+ fmt::print( stderr, "[e] number of arguments of a `{}` instance is not 2\n", module_name );
+
+ signal<Ntk> fi = ntk_.get_constant( false );
+ std::string lhs;
+ for ( auto const& arg : args )
  {
- if ( !num_args_equals( 2u ) )
- fmt::print( stderr, "[e] number of arguments of a `{}` instance is not 2\n", module_name );
-
- signal<Ntk> fi;
- std::string lhs;
- for ( auto const& arg : args )
+ if ( arg.first == ".i" )
  {
- if ( arg.first == ".i" )
- fi = signals_[arg.second];
- else if ( arg.first == ".o" )
- lhs = arg.second;
+ if ( signals_.find( arg.second ) == signals_.end() )
+ fmt::print( stderr, "[w] undefined signal {} assigned 0\n", arg.second );
  else
- fmt::print( stderr, "[e] unknown argument {} to a `{}` instance\n", arg.first, module_name );
+ fi = signals_[arg.second];
  }
- if ( module_name == "inverter" )
- fi = ntk_.create_not( fi );
- signals_[lhs] = ntk_.create_buf( fi );
- return;
+ else if ( arg.first == ".o" )
+ lhs = arg.second;
+ else
+  fmt::print( stderr, "[e] unknown argument {} to a `{}` instance\n", arg.first, module_name );
  }
+ if ( module_name == "inverter" )
+ fi = ntk_.create_not( fi );
+ signals_[lhs] = ntk_.create_buf( fi );
  }
-
+ }
+ else
+ {
  fmt::print( stderr, "[e] unknown module name {}\n", module_name );
  }
  }
@@ -391,6 +401,26 @@ class verilog_reader : public lorina::verilog_reader
  {
  ntk_.create_po( signals_[o], o );
  }
+
+ if constexpr ( has_set_output_name_v<Ntk> )
+ {
+ uint32_t ctr{0u};
+ for ( auto const& output_name : output_names_ )
+ {
+ if ( output_name.second == 1u )
+ {
+ ntk_.set_output_name( ctr++, output_name.first );
+ }
+ else
+ {
+ for ( auto i = 0u; i < output_name.second; ++i )
+ {
+ ntk_.set_output_name( ctr++, fmt::format( "{}[{}]", output_name.first, i ) );
+ }
+ }
+ }
+ assert( ctr == ntk_.num_pos() );
+ }
  }
 
  const std::string& name() const

include/mockturtle/io/write_verilog.hpp

@@ -140,8 +140,26 @@ void write_verilog( Ntk const& ntk, std::ostream& os, write_verilog_params const
  std::vector<std::string> xs, inputs;
  if ( ps.input_names.empty() )
  {
- for ( auto i = 0u; i < ntk.num_pis(); ++i )
- xs.emplace_back( fmt::format( "x{}", i ) );
+ if constexpr ( has_has_name_v<Ntk> && has_get_name_v<Ntk> )
+ {
+ ntk.foreach_pi( [&]( auto const& i, uint32_t index ){
+ if ( ntk.has_name( ntk.make_signal( i ) ) )
+ {
+ xs.emplace_back( ntk.get_name( ntk.make_signal( i ) ) );
+ }
+ else
+ {
+ xs.emplace_back( fmt::format( "x{}", index ) );
+ }
+ });
+ }
+ else
+ {
+ for ( auto i = 0u; i < ntk.num_pis(); ++i )
+ {
+ xs.emplace_back( fmt::format( "x{}", i ) );
+ }
+ }
  inputs = xs;
  }
  else
@@ -165,8 +183,26 @@ void write_verilog( Ntk const& ntk, std::ostream& os, write_verilog_params const
  std::vector<std::string> ys, outputs;
  if ( ps.output_names.empty() )
  {
- for ( auto i = 0u; i < ntk.num_pos(); ++i )
- ys.emplace_back( fmt::format( "y{}", i ) );
+ if constexpr ( has_has_output_name_v<Ntk> && has_get_output_name_v<Ntk> )
+ {
+ ntk.foreach_po( [&]( auto const& o, uint32_t index ){
+ if ( ntk.has_output_name( index ) )
+ {
+ ys.emplace_back( ntk.get_output_name( index ) );
+ }
+ else
+ {
+ ys.emplace_back( fmt::format( "y{}", index ) );
+ }
+ });
+ }
+ else
+ {
+ for ( auto i = 0u; i < ntk.num_pos(); ++i )
+ {
+ ys.emplace_back( fmt::format( "y{}", i ) );
+ }
+ }
  outputs = ys;
  }
  else

include/mockturtle/networks/buffered.hpp

@@ -35,6 +35,7 @@
 #include "../traits.hpp"
 #include "aig.hpp"
 #include "mig.hpp"
+#include "../views/names_view.hpp"
 
 namespace mockturtle
 {
@@ -521,7 +522,13 @@ class buffered_mig_network : public mig_network
 template<>
 struct is_buffered_network_type<buffered_aig_network> : std::true_type {};
 
+template<>
+struct is_buffered_network_type<names_view<buffered_aig_network>> : std::true_type {};
+
 template<>
 struct is_buffered_network_type<buffered_mig_network> : std::true_type {};
 
+template<>
+struct is_buffered_network_type<names_view<buffered_mig_network>> : std::true_type {};
+
 } // namespace mockturtle

include/mockturtle/utils/name_utils.hpp

@@ -28,6 +28,7 @@
  \brief Utility functions to restore network names after optimization.
 
  \author Marcel Walter
+ \author Siang-Yun Lee
 */
 
 #pragma once
@@ -106,4 +107,56 @@ void restore_names( const NtkSrc& ntk_src, NtkDest& ntk_dest, node_map<signal<Nt
  }
 }
 
+/*! \brief Restore PI and PO names, matching by order.
+ *
+ * **Required network functions for NtkSrc:**
+ * - `foreach_pi`
+ * - `foreach_po`
+ * - `num_pis`
+ * - `num_pos`
+ * - `has_name`
+ * - `get_name`
+ * - `make_signal`
+ * - `has_output_name`
+ * - `get_output_name`
+ * 
+ * **Required network functions for NtkDest:**
+ * - `foreach_pi`
+ * - `num_pis`
+ * - `num_pos`
+ * - `set_name`
+ * - `make_signal`
+ * - `set_output_name`
+ *
+ * \param ntk_src The source logic network, which potentially has named signals
+ * \param ntk_dest The destination logic network, whose names are to be restored
+ */
+template<typename NtkSrc, typename NtkDest>
+void restore_pio_names_by_order( const NtkSrc& ntk_src, NtkDest& ntk_dest )
+{
+ static_assert( is_network_type_v<NtkSrc>, "NtkSrc is not a network type" );
+ static_assert( is_network_type_v<NtkDest>, "NtkDest is not a network type" );
+ static_assert( has_has_name_v<NtkSrc> && has_get_name_v<NtkSrc>, "NtkSrc does not implement the has_name and/or get_name functions" );
+ static_assert( has_has_output_name_v<NtkSrc> && has_get_output_name_v<NtkSrc>, "NtkSrc does not implement the has_output_name and/or get_output_name functions" );
+ static_assert( has_set_name_v<NtkDest> && has_set_output_name_v<NtkDest>, "NtkDest does not implement the set_name and/or set_output_name functions" );
+
+ assert( ntk_src.num_pis() == ntk_dest.num_pis() );
+ assert( ntk_src.num_pos() == ntk_dest.num_pos() );
+
+ std::vector<std::string> pi_names( ntk_src.num_pis(), "" );
+ ntk_src.foreach_pi( [&]( auto const& n, auto i ){
+ if ( ntk_src.has_name( ntk_src.make_signal( n ) ) )
+ pi_names[i] = ntk_src.get_name( ntk_src.make_signal( n ) );
+ });
+ ntk_dest.foreach_pi( [&]( auto const& n, auto i ){
+ if ( pi_names[i] != "" )
+ ntk_dest.set_name( ntk_dest.make_signal( n ), pi_names[i] );
+ });
+
+ ntk_src.foreach_po( [&]( auto const& f, auto i ){
+ if ( ntk_src.has_output_name( i ) )
+ ntk_dest.set_output_name( i, ntk_src.get_output_name( i ) );
+ });
+}
+
 } // namespace mockturtle

lib/bill/bill/sat/solver/abc/system.h

@@ -21,7 +21,6 @@ OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWA
 #ifndef Abc_Glucose_System_h
 #define Abc_Glucose_System_h
 
-
 #include "IntTypes.h"
 
 ABC_NAMESPACE_CXX_HEADER_START

lib/bill/bill/sat/solver/maple.hpp

@@ -1438,7 +1438,6 @@ OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWA
 #define Minisat_System_h
 
 
-
 //-------------------------------------------------------------------------------------------------
 
 namespace Maple {
@@ -4578,7 +4577,7 @@ static void SIGALRM_switch(int signum) { switch_mode = true; }
 // NOTE: assumptions passed in member-variable 'assumptions'.
 inline lbool Solver::solve_()
 {
- std::signal(SIGALRM, SIGALRM_switch);
+ ::signal(SIGALRM, SIGALRM_switch);
  alarm(2500);
 
  model.clear();

lib/lorina/lorina/bench.hpp

@@ -177,23 +177,46 @@ static std::regex gate_asgn( R"((.*)\s+=\s+(.*))" );
 {
  return_code result = return_code::success;
 
- const auto dispatch_function = [&]( std::vector<std::string> inputs, std::string output, std::string type )
- {
- if ( type == "" )
- {
- reader.on_assign( inputs.front(), output );
- }
- else if ( type == "DFF" )
- {
- reader.on_dff( inputs.front(), output );
- }
- else
- {
- reader.on_gate( inputs, output, type );
- }
- };
-
- detail::call_in_topological_order<std::vector<std::string>, std::string, std::string> on_action( dispatch_function );
+ /* Function signature */
+ using GateFn = detail::Func<
+ std::vector<std::string>,
+ std::string,
+ std::string
+ >;
+
+ /* Parameter maps */
+ using GateParamMap = detail::ParamPackMap<
+ /* Key */
+ std::string,
+ /* Params */
+ std::vector<std::string>,
+ std::string,
+ std::string
+ >;
+
+ constexpr static const int GATE_FN{0};
+
+ using ParamMaps = detail::ParamPackMapN<GateParamMap>;
+ using PackedFns = detail::FuncPackN<GateFn>;
+
+ detail::call_in_topological_order<PackedFns, ParamMaps>
+ on_action( PackedFns( GateFn( [&]( std::vector<std::string> inputs,
+ std::string output,
+ std::string type )
+ {
+ if ( type == "" )
+ {
+ reader.on_assign( inputs.front(), output );
+ }
+ else if ( type == "DFF" )
+ {
+ reader.on_dff( inputs.front(), output );
+ }
+ else
+ {
+ reader.on_gate( inputs, output, type );
+ }
+ } ) ) );
  on_action.declare_known( "vdd" );
  on_action.declare_known( "gnd" );
 
@@ -226,7 +249,7 @@ static std::regex gate_asgn( R"((.*)\s+=\s+(.*))" );
  const auto type = detail::trim_copy( m[2] );
  const auto args = detail::trim_copy( m[3] );
  const auto inputs = detail::split( args, "," );
- on_action.call_deferred( inputs, output, inputs, output, type );
+ on_action.call_deferred<GATE_FN>( inputs, { output }, std::make_tuple( inputs, output, type ) );
  return true;
  }
 
@@ -237,7 +260,7 @@ static std::regex gate_asgn( R"((.*)\s+=\s+(.*))" );
  const auto arg = detail::trim_copy( m[2] );
  reader.on_dff_input( output );
  on_action.declare_known( output );
- on_action.call_deferred( { arg }, output, { arg }, output, "DFF" );
+ on_action.call_deferred<GATE_FN>( { arg }, { output }, std::make_tuple( std::vector<std::string>{ arg }, output, "DFF" ) );
  return true;
  }
 
@@ -248,7 +271,7 @@ static std::regex gate_asgn( R"((.*)\s+=\s+(.*))" );
  const auto type = detail::trim_copy( m[2] );
  const auto args = detail::trim_copy( m[3] );
  const auto inputs = detail::split( args, "," );
- on_action.call_deferred( inputs, output, inputs, output, type );
+ on_action.call_deferred<GATE_FN>( inputs, { output }, std::make_tuple( inputs, output, type ) );
  return true;
  }
 
@@ -257,7 +280,7 @@ static std::regex gate_asgn( R"((.*)\s+=\s+(.*))" );
  {
  const auto output = detail::trim_copy( m[1] );
  const auto input = detail::trim_copy( m[2] );
- on_action.call_deferred( { input }, output, { input }, output, "" );
+ on_action.call_deferred<GATE_FN>( { input }, { output }, std::make_tuple( std::vector<std::string>{ input }, output, "" ) );
  return true;
  }
 
@@ -273,7 +296,10 @@ static std::regex gate_asgn( R"((.*)\s+=\s+(.*))" );
  /* check dangling objects */
  const auto& deps = on_action.unresolved_dependencies();
  if ( deps.size() > 0 )
+ {
  result = return_code::parse_error;
+ }
+
  for ( const auto& r : deps )
  {
  if ( diag )