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[CacheOp] should respond for cache ecc op
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@fawangZ @Siudya
fawangZ authored and Siudya committed Jan 22, 2024
1 parent fc80630 commit 519121b
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Showing 2 changed files with 36 additions and 36 deletions.
36 changes: 18 additions & 18 deletions src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -512,14 +512,14 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
}
cacheOpShouldResp := true.B
}
// when (io.cacheOp_req_dup(0).valid && CacheInstrucion.isReadDataECC(io.cacheOp_req_bits_opCode_dup(0))) {
when (io.cacheOp_req_dup(0).valid && CacheInstrucion.isReadDataECC(io.cacheOp_req_bits_opCode_dup(0))) {
// for (bank_index <- 0 until (DCacheBanks / 3)) {
// val ecc_bank = ecc_banks(bank_index)
// ecc_bank.io.r.req.valid := true.B
// ecc_bank.io.r.req.bits.setIdx := io.cacheOp.req.bits.index
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}
when(io.cacheOp_req_dup(1).valid && CacheInstrucion.isWriteData(io.cacheOp_req_bits_opCode_dup(1))) {
for (bank_index <- 0 until (DCacheBanks / 3)) {
val data_bank = data_banks(bank_index)
Expand All @@ -530,7 +530,7 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
}
cacheOpShouldResp := true.B
}
// when(io.cacheOp_req_dup(2).valid && CacheInstrucion.isWriteDataECC(io.cacheOp_req_bits_opCode_dup(2))){
when(io.cacheOp_req_dup(2).valid && CacheInstrucion.isWriteDataECC(io.cacheOp_req_bits_opCode_dup(2))){
// for (bank_index <- 0 until (DCacheBanks / 3)) {
// val ecc_bank = ecc_banks(bank_index)
// ecc_bank.io.w.req.valid := true.B
Expand All @@ -540,8 +540,8 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
// waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// )
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}


when(io.cacheOp_req_dup(3).valid && CacheInstrucion.isReadData(io.cacheOp_req_bits_opCode_dup(3))) {
Expand All @@ -553,14 +553,14 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
}
cacheOpShouldResp := true.B
}
// when (io.cacheOp_req_dup(4).valid && CacheInstrucion.isReadDataECC(io.cacheOp_req_bits_opCode_dup(4))) {
when (io.cacheOp_req_dup(4).valid && CacheInstrucion.isReadDataECC(io.cacheOp_req_bits_opCode_dup(4))) {
// for (bank_index <- (DCacheBanks / 3) until ((DCacheBanks / 3) * 2)) {
// val ecc_bank = ecc_banks(bank_index)
// ecc_bank.io.r.req.valid := true.B
// ecc_bank.io.r.req.bits.setIdx := io.cacheOp.req.bits.index
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}
when(io.cacheOp_req_dup(5).valid && CacheInstrucion.isWriteData(io.cacheOp_req_bits_opCode_dup(5))) {
for (bank_index <- (DCacheBanks / 3) until ((DCacheBanks / 3) * 2)) {
val data_bank = data_banks(bank_index)
Expand All @@ -571,7 +571,7 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
}
cacheOpShouldResp := true.B
}
// when(io.cacheOp_req_dup(6).valid && CacheInstrucion.isWriteDataECC(io.cacheOp_req_bits_opCode_dup(6))){
when(io.cacheOp_req_dup(6).valid && CacheInstrucion.isWriteDataECC(io.cacheOp_req_bits_opCode_dup(6))){
// for (bank_index <- (DCacheBanks / 3) until ((DCacheBanks / 3) * 2)) {
// val ecc_bank = ecc_banks(bank_index)
// ecc_bank.io.w.req.valid := true.B
Expand All @@ -581,8 +581,8 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
// waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// )
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}

when(io.cacheOp_req_dup(7).valid && CacheInstrucion.isReadData(io.cacheOp_req_bits_opCode_dup(7))) {
for (bank_index <- ((DCacheBanks / 3) * 2) until DCacheBanks) {
Expand All @@ -593,14 +593,14 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
}
cacheOpShouldResp := true.B
}
// when (io.cacheOp_req_dup(8).valid && CacheInstrucion.isReadDataECC(io.cacheOp_req_bits_opCode_dup(8))) {
when (io.cacheOp_req_dup(8).valid && CacheInstrucion.isReadDataECC(io.cacheOp_req_bits_opCode_dup(8))) {
// for (bank_index <- ((DCacheBanks / 3) * 2) until DCacheBanks) {
// val ecc_bank = ecc_banks(bank_index)
// ecc_bank.io.r.req.valid := true.B
// ecc_bank.io.r.req.bits.setIdx := io.cacheOp.req.bits.index
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}
when(io.cacheOp_req_dup(9).valid && CacheInstrucion.isWriteData(io.cacheOp_req_bits_opCode_dup(9))) {
for (bank_index <- ((DCacheBanks / 3) * 2) until DCacheBanks) {
val data_bank = data_banks(bank_index)
Expand All @@ -611,7 +611,7 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
}
cacheOpShouldResp := true.B
}
// when(io.cacheOp_req_dup(10).valid && CacheInstrucion.isWriteDataECC(io.cacheOp_req_bits_opCode_dup(10))){
when(io.cacheOp_req_dup(10).valid && CacheInstrucion.isWriteDataECC(io.cacheOp_req_bits_opCode_dup(10))){
// for (bank_index <- ((DCacheBanks / 3) * 2) until DCacheBanks) {
// val ecc_bank = ecc_banks(bank_index)
// ecc_bank.io.w.req.valid := true.B
Expand All @@ -621,8 +621,8 @@ class BankedDataArray(parentName: String = "Unknown")(implicit p: Parameters) ex
// waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// )
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}

io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp)
for (bank_index <- 0 until DCacheBanks) {
Expand Down
36 changes: 18 additions & 18 deletions src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -367,14 +367,14 @@ class DuplicatedTagArray(readPorts: Int, parentName:String = "Unknown")(implicit
}
cacheOpShouldResp := true.B
}
// when (io.cacheOp_req_dup(0).valid && isReadTagECC(io.cacheOp_req_bits_opCode_dup(0))) {
when (io.cacheOp_req_dup(0).valid && isReadTagECC(io.cacheOp_req_bits_opCode_dup(0))) {
// for (i <- 0 until (readPorts / 3)) {
// array(i).io.ecc_read.valid := true.B
// array(i).io.ecc_read.bits.idx := io.cacheOp.req.bits.index
// array(i).io.ecc_read.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}
when (io.cacheOp_req_dup(1).valid && isWriteTag(io.cacheOp_req_bits_opCode_dup(1))){
for (i <- 0 until (readPorts / 3)) {
array(i).io.write.valid := true.B
Expand All @@ -384,15 +384,15 @@ class DuplicatedTagArray(readPorts: Int, parentName:String = "Unknown")(implicit
}
cacheOpShouldResp := true.B
}
// when(io.cacheOp_req_dup(2).valid && isWriteTagECC(io.cacheOp_req_bits_opCode_dup(2))){
when(io.cacheOp_req_dup(2).valid && isWriteTagECC(io.cacheOp_req_bits_opCode_dup(2))){
// for (i <- 0 until (readPorts / 3)) {
// array(i).io.ecc_write.valid := true.B
// array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index
// array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}


when (io.cacheOp_req_dup(3).valid && isReadTag(io.cacheOp_req_bits_opCode_dup(3))){
Expand All @@ -403,14 +403,14 @@ class DuplicatedTagArray(readPorts: Int, parentName:String = "Unknown")(implicit
}
cacheOpShouldResp := true.B
}
// when (io.cacheOp_req_dup(4).valid && isReadTagECC(io.cacheOp_req_bits_opCode_dup(4))) {
when (io.cacheOp_req_dup(4).valid && isReadTagECC(io.cacheOp_req_bits_opCode_dup(4))) {
// for (i <- (readPorts / 3) until ((readPorts / 3) * 2)) {
// array(i).io.ecc_read.valid := true.B
// array(i).io.ecc_read.bits.idx := io.cacheOp.req.bits.index
// array(i).io.ecc_read.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}
when (io.cacheOp_req_dup(5).valid && isWriteTag(io.cacheOp_req_bits_opCode_dup(5))){
for (i <- (readPorts / 3) until ((readPorts / 3) * 2)) {
array(i).io.write.valid := true.B
Expand All @@ -420,15 +420,15 @@ class DuplicatedTagArray(readPorts: Int, parentName:String = "Unknown")(implicit
}
cacheOpShouldResp := true.B
}
// when(io.cacheOp_req_dup(6).valid && isWriteTagECC(io.cacheOp_req_bits_opCode_dup(6))){
when(io.cacheOp_req_dup(6).valid && isWriteTagECC(io.cacheOp_req_bits_opCode_dup(6))){
// for (i <- (readPorts / 3) until ((readPorts / 3) * 2)) {
// array(i).io.ecc_write.valid := true.B
// array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index
// array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}

when (io.cacheOp_req_dup(7).valid && isReadTag(io.cacheOp_req_bits_opCode_dup(7))){
for (i <- ((readPorts / 3) * 2) until readPorts) {
Expand All @@ -438,14 +438,14 @@ class DuplicatedTagArray(readPorts: Int, parentName:String = "Unknown")(implicit
}
cacheOpShouldResp := true.B
}
// when (io.cacheOp_req_dup(8).valid && isReadTagECC(io.cacheOp_req_bits_opCode_dup(8))) {
when (io.cacheOp_req_dup(8).valid && isReadTagECC(io.cacheOp_req_bits_opCode_dup(8))) {
// for (i <- ((readPorts / 3) * 2) until readPorts) {
// array(i).io.ecc_read.valid := true.B
// array(i).io.ecc_read.bits.idx := io.cacheOp.req.bits.index
// array(i).io.ecc_read.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}
when (io.cacheOp_req_dup(9).valid && isWriteTag(io.cacheOp_req_bits_opCode_dup(9))){
for (i <- ((readPorts / 3) * 2) until readPorts) {
array(i).io.write.valid := true.B
Expand All @@ -455,15 +455,15 @@ class DuplicatedTagArray(readPorts: Int, parentName:String = "Unknown")(implicit
}
cacheOpShouldResp := true.B
}
// when(io.cacheOp_req_dup(10).valid && isWriteTagECC(io.cacheOp_req_bits_opCode_dup(10))){
when(io.cacheOp_req_dup(10).valid && isWriteTagECC(io.cacheOp_req_bits_opCode_dup(10))){
// for (i <- ((readPorts / 3) * 2) until readPorts) {
// array(i).io.ecc_write.valid := true.B
// array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index
// array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0))
// array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc
// }
// cacheOpShouldResp := true.B
// }
cacheOpShouldResp := true.B
}

io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp)
io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, array(0).io.resp(RegNext(io.cacheOp.req.bits.wayNum)), 0.U)
Expand Down

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