Merge pull request juribeparada#144 from g4klx/master

Add M17 support

ADF7021.h

@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2020 by Jonathan Naylor G4KLX
  * Copyright (C) 2016 by Jim McLaughlin KI6ZUM
  * Copyright (C) 2016,2017,2018 by Andy Uribe CA6JAU
  * Copyright (C) 2017 by Danilo DB4PLE 
@@ -52,7 +53,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 // Support for ADF7021-N version: 
 // #define ADF7021_N_VER
 
-// Enable AFC support for DMR, YSF and P25 (experimental):
+// Enable AFC support for DMR, YSF, P25, and M17 (experimental):
 // (AFC is already enabled by default in D-Star)
 // #define ADF7021_ENABLE_4FSK_AFC
 
@@ -65,7 +66,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 // R = 4
 // DEMOD_CLK = 2.4576 MHz (DSTAR)
 // DEMOD_CLK = 4.9152 MHz (DMR, YSF_L, P25)
-// DEMOD_CLK = 7.3728 MHz (YSF_H)
+// DEMOD_CLK = 7.3728 MHz (YSF_H, M17)
 // DEMOD CLK = 3.6864 MHz (NXDN)
 // DEMOD_CLK = 7.3728 MHz (POCSAG)
 #define ADF7021_PFD 3686400.0
@@ -87,6 +88,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DEV_P25 22U
 #endif
 #define ADF7021_DEV_NXDN 13U
+#define ADF7021_DEV_M17 28U
 #define ADF7021_DEV_POCSAG 160U
 
 // TX/RX CLOCK register (REG 03)
@@ -97,12 +99,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_REG3_YSF_H 0x2A4C0493
 #define ADF7021_REG3_P25 0x2A4C04D3
 #define ADF7021_REG3_NXDN 0x2A4C04D3
+#define ADF7021_REG3_M17 0x2A4C04D3
 #else
 #define ADF7021_REG3_DMR 0x2A4C80D3
 #define ADF7021_REG3_YSF_L 0x2A4C80D3
 #define ADF7021_REG3_YSF_H 0x2A4CC093
 #define ADF7021_REG3_P25 0x2A4C80D3
 #define ADF7021_REG3_NXDN 0x2A4CC113
+#define ADF7021_REG3_M17 0x2A4CC093
 #endif
 #define ADF7021_REG3_POCSAG 0x2A4F0093
 
@@ -114,6 +118,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DISC_BW_YSF_H 516U // K=28
 #define ADF7021_DISC_BW_P25 394U // K=32
 #define ADF7021_DISC_BW_NXDN 295U // K=32
+#define ADF7021_DISC_BW_M17 590U // K=32
 #define ADF7021_DISC_BW_POCSAG 406U // K=22
 
 // Post demodulator bandwith (REG 04)
@@ -122,6 +127,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_POST_BW_YSF 20U
 #define ADF7021_POST_BW_P25 6U
 #define ADF7021_POST_BW_NXDN 7U
+#define ADF7021_POST_BW_M17 7U // Test
 #define ADF7021_POST_BW_POCSAG 1U
 
 // IF filter (REG 05)
@@ -139,34 +145,39 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_REG10_YSF 0x01FE473A
 #define ADF7021_REG10_P25 0x01FE473A
 #define ADF7021_REG10_NXDN 0x01FE473A
+#define ADF7021_REG10_M17 0x01FE473A
 #if defined(ADF7021_AFC_POS)
 #define AFC_OFFSET_DMR -250
 #define AFC_OFFSET_YSF -250
 #define AFC_OFFSET_P25 -250
 #define AFC_OFFSET_NXDN -250
+#define AFC_OFFSET_M17 -250
 #else
 #define AFC_OFFSET_DMR 250
 #define AFC_OFFSET_YSF 250
 #define AFC_OFFSET_P25 250
 #define AFC_OFFSET_NXDN 250
+#define AFC_OFFSET_M17 250
 #endif
 #else
 #define ADF7021_REG10_DMR 0x049E472A
 #define ADF7021_REG10_YSF 0x049E472A
 #define ADF7021_REG10_P25 0x049E472A
 #define ADF7021_REG10_NXDN 0x049E472A
+#define ADF7021_REG10_M17 0x049E472A
 #define AFC_OFFSET_DMR 0
 #define AFC_OFFSET_YSF 0
 #define AFC_OFFSET_P25 0
 #define AFC_OFFSET_NXDN 0
+#define AFC_OFFSET_M17 0
 #endif
 
 /****** Support for 12.2880 MHz TCXO ******/
 #elif defined(ADF7021_12_2880)
 
 // R = 2
 // DEMOD_CLK = 2.4576 MHz (DSTAR)
-// DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25)
+// DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25, M17)
 // DEMOD_CLK = 3.0720 MHz (NXDN)
 // DEMOD_CLK = 6.1440 MHz (POCSAG)
 #define ADF7021_PFD 6144000.0
@@ -188,6 +199,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DEV_P25 13U
 #endif
 #define ADF7021_DEV_NXDN 8U
+#define ADF7021_DEV_M17 17U
 #define ADF7021_DEV_POCSAG 96U
 
 // TX/RX CLOCK register (REG 03)
@@ -198,12 +210,14 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_REG3_YSF_H 0x29EC0493
 #define ADF7021_REG3_P25 0x29EC0493
 #define ADF7021_REG3_NXDN 0x29EC0493
+#define ADF7021_REG3_M17 0x29EC0493
 #else
 #define ADF7021_REG3_DMR 0x29ECA093
 #define ADF7021_REG3_YSF_L 0x29ECA093
 #define ADF7021_REG3_YSF_H 0x29ECA093
 #define ADF7021_REG3_P25 0x29ECA093
 #define ADF7021_REG3_NXDN 0x29ECA113
+#define ADF7021_REG3_M17 0x29ECA093
 #endif
 #define ADF7021_REG3_POCSAG 0x29EE8093
 
@@ -215,6 +229,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DISC_BW_YSF_H 430U // K=28
 #define ADF7021_DISC_BW_P25 493U // K=32
 #define ADF7021_DISC_BW_NXDN 246U // K=32
+#define ADF7021_DISC_BW_M17 492U // K=32
 #define ADF7021_DISC_BW_POCSAG 338U // K=22
 
 // Post demodulator bandwith (REG 04)
@@ -223,6 +238,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_POST_BW_YSF 20U
 #define ADF7021_POST_BW_P25 6U
 #define ADF7021_POST_BW_NXDN 8U
+#define ADF7021_POST_BW_M17 8U // Test
 #define ADF7021_POST_BW_POCSAG 1U
 
 // IF filter (REG 05)
@@ -240,26 +256,31 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_REG10_YSF 0x01FE557A
 #define ADF7021_REG10_P25 0x01FE557A
 #define ADF7021_REG10_NXDN 0x01FE557A
+#define ADF7021_REG10_M17 0x01FE557A
 #if defined(ADF7021_AFC_POS)
 #define AFC_OFFSET_DMR -250
 #define AFC_OFFSET_YSF -250
 #define AFC_OFFSET_P25 -250
 #define AFC_OFFSET_NXDN -250
+#define AFC_OFFSET_M17 -250
 #else
 #define AFC_OFFSET_DMR 250
 #define AFC_OFFSET_YSF 250
 #define AFC_OFFSET_P25 250
 #define AFC_OFFSET_NXDN 250
+#define AFC_OFFSET_M17 250
 #endif
 #else
 #define ADF7021_REG10_DMR 0x049E556A
 #define ADF7021_REG10_YSF 0x049E556A
 #define ADF7021_REG10_P25 0x049E556A
 #define ADF7021_REG10_NXDN 0x049E556A
+#define ADF7021_REG10_M17 0x049E556A
 #define AFC_OFFSET_DMR 0
 #define AFC_OFFSET_YSF 0
 #define AFC_OFFSET_P25 0
 #define AFC_OFFSET_NXDN 0
+#define AFC_OFFSET_M17 0
 #endif
 
 #endif
@@ -273,6 +294,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_SLICER_TH_YSF_H 69U
 #define ADF7021_SLICER_TH_P25 43U
 #define ADF7021_SLICER_TH_NXDN 26U
+#define ADF7021_SLICER_TH_M17 59U // Test
 
 #else
 
@@ -282,6 +304,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_SLICER_TH_YSF_H 75U
 #define ADF7021_SLICER_TH_P25 47U
 #define ADF7021_SLICER_TH_NXDN 26U
+#define ADF7021_SLICER_TH_M17 59U // Test
 
 #endif
 

Config.h

@@ -95,6 +95,9 @@
 // Use the YSF and P25 LEDs for NXDN
 // #define USE_ALTERNATE_NXDN_LEDS
 
+// Use the D-Star and P25 LEDs for M17
+// #define USE_ALTERNATE_M17_LEDS
+
 // Use the D-Star and DMR LEDs for POCSAG
 // #define USE_ALTERNATE_POCSAG_LEDS
 

Globals.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
+ * Copyright (C) 2015,2016,2020 by Jonathan Naylor G4KLX
  * Copyright (C) 2016,2017,2018,2019 by Andy Uribe CA6JAU
  * Copyright (C) 2019 by Florian Wolters DF2ET
  *
@@ -42,6 +42,7 @@ enum MMDVM_STATE {
  STATE_P25 = 4,
  STATE_NXDN = 5,
  STATE_POCSAG = 6,
+ STATE_M17 = 7,
 
  // Dummy states start at 90
  STATE_DMRDMO1K = 92,
@@ -77,6 +78,8 @@ const uint8_t MARK_NONE = 0x00U;
 #include "YSFTX.h"
 #include "P25RX.h"
 #include "P25TX.h"
+#include "M17RX.h"
+#include "M17TX.h"
 #include "NXDNRX.h"
 #include "NXDNTX.h"
 #include "POCSAGTX.h"
@@ -103,6 +106,7 @@ extern bool m_dmrEnable;
 extern bool m_ysfEnable;
 extern bool m_p25Enable;
 extern bool m_nxdnEnable;
+extern bool m_m17Enable;
 extern bool m_pocsagEnable;
 
 extern bool m_duplex;
@@ -133,6 +137,9 @@ extern CYSFTX ysfTX;
 extern CP25RX p25RX;
 extern CP25TX p25TX;
 
+extern CM17RX m17RX;
+extern CM17TX m17TX;
+
 extern CNXDNRX nxdnRX;
 extern CNXDNTX nxdnTX;
 

IO.cpp

@@ -1,8 +1,8 @@
 /*
- * Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
+ * Copyright (C) 2015,2016,2020 by Jonathan Naylor G4KLX
  * Copyright (C) 2016,2017,2018,2019,2020 by Andy Uribe CA6JAU
  * Copyright (C) 2017 by Danilo DB4PLE
-
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -51,6 +51,7 @@ m_int2counter(0U)
  YSF_pin(LOW);
  P25_pin(LOW);
  NXDN_pin(LOW);
+ M17_pin(LOW);
  POCSAG_pin(LOW);
  COS_pin(LOW);
  DEB_pin(LOW);
@@ -89,6 +90,7 @@ void CIO::selfTest()
  YSF_pin(ledValue);
  P25_pin(ledValue);
  NXDN_pin(ledValue);
+ M17_pin(ledValue);
  POCSAG_pin(ledValue);
  COS_pin(ledValue);
 
@@ -111,7 +113,7 @@ void CIO::process()
  if (m_started) {
  // Two seconds timeout
  if (m_watchdog >= 19200U) {
- if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF || m_modemState == STATE_P25 || m_modemState == STATE_NXDN) {
+ if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF || m_modemState == STATE_P25 || m_modemState == STATE_NXDN || m_modemState == STATE_M17) {
  m_modemState = STATE_IDLE;
  setMode(m_modemState);
  }
@@ -178,6 +180,8 @@ void CIO::process()
  scantime = SCAN_TIME;
  else if(m_modemState_prev == STATE_NXDN)
  scantime = SCAN_TIME;
+ else if(m_modemState_prev == STATE_M17)
+ scantime = SCAN_TIME;
  else
  scantime = SCAN_TIME;
 
@@ -221,6 +225,9 @@ void CIO::process()
  case STATE_NXDN:
  nxdnRX.databit(bit);
  break;
+ case STATE_M17:
+ m17RX.databit(bit);
+ break;
  default:
  break;
  }
@@ -252,6 +259,10 @@ void CIO::start()
  m_Modes[m_TotalModes] = STATE_NXDN;
  m_TotalModes++;
  }
+ if(m_m17Enable) {
+ m_Modes[m_TotalModes] = STATE_M17;
+ m_TotalModes++;
+ }
 
 #if defined(ENABLE_SCAN_MODE)
  if(m_TotalModes > 1U)
@@ -412,6 +423,14 @@ void CIO::setMode(MMDVM_STATE modemState)
 #if defined(USE_ALTERNATE_NXDN_LEDS)
  }
 #endif
+#if defined(USE_ALTERNATE_M17_LEDS)
+ if (modemState != STATE_M17) {
+#endif
+ YSF_pin(modemState == STATE_DSTAR);
+ P25_pin(modemState == STATE_P25);
+#if defined(USE_ALTERNATE_M17_LEDS)
+ }
+#endif
 #if defined(USE_ALTERNATE_NXDN_LEDS)
  if (modemState != STATE_YSF && modemState != STATE_P25) {
 #endif
@@ -426,6 +445,13 @@ void CIO::setMode(MMDVM_STATE modemState)
 #if defined(USE_ALTERNATE_POCSAG_LEDS)
  }
 #endif
+#if defined(USE_ALTERNATE_M17_LEDS)
+ if (modemState != STATE_DSTAR && modemState != STATE_P25) {
+#endif
+ M17_pin(modemState == STATE_M17);
+#if defined(USE_ALTERNATE_M17_LEDS)
+ }
+#endif
 }
 
 void CIO::setDecode(bool dcd)

IO.h

@@ -1,8 +1,8 @@
 /*
- * Copyright (C) 2015,2016 by Jonathan Naylor G4KLX
+ * Copyright (C) 2015,2016,2020 by Jonathan Naylor G4KLX
  * Copyright (C) 2016,2017,2018,2019,2020 by Andy Uribe CA6JAU
  * Copyright (C) 2017 by Danilo DB4PLE
-
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -98,6 +98,7 @@ class CIO {
  void YSF_pin(bool on);
  void P25_pin(bool on);
  void NXDN_pin(bool on);
+ void M17_pin(bool on);
  void POCSAG_pin(bool on);
  void COS_pin(bool on);
  void interrupt(void);
@@ -141,7 +142,7 @@ class CIO {
 #endif
  void start(void);
  void startInt(void);
- void setDeviations(uint8_t dstarTXLevel, uint8_t dmrTXLevel, uint8_t ysfTXLevel, uint8_t p25TXLevel, uint8_t nxdnTXLevel, uint8_t pocsagTXLevel, bool ysfLoDev);
+ void setDeviations(uint8_t dstarTXLevel, uint8_t dmrTXLevel, uint8_t ysfTXLevel, uint8_t p25TXLevel, uint8_t nxdnTXLevel, uint8_t m17TXLevel, uint8_t pocsagTXLevel, bool ysfLoDev);
  void updateCal(void);
 
 #if defined(SEND_RSSI_DATA)
@@ -162,6 +163,7 @@ class CIO {
  uint16_t devYSF(void);
  uint16_t devP25(void);
  uint16_t devNXDN(void);
+ uint16_t devM17(void);
  uint16_t devPOCSAG(void);
  void printConf();
 #endif
@@ -181,7 +183,7 @@ class CIO {
  uint32_t m_scanPauseCnt;
  uint8_t m_scanPos;
  uint8_t m_TotalModes;
- MMDVM_STATE m_Modes[5];
+ MMDVM_STATE m_Modes[6];
  bool m_ledValue;
  volatile uint32_t m_watchdog;
  volatile uint16_t m_int1counter;