Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

SERV - The SErial RISC-V CPU

A lightweight TUI application to view and query tabular data files, such as CSV, TSV, and parquet.

A command-line tool for displaying vcd waveforms.

A simple terminal UI for search and replace, ala VS Code.

RISC-V BSV Specification

An incremental parsing system for programming tools

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

🔥 A cross-platform build utility based on Lua

A list of Hanabi strategies

Haskell library for hardware description

View 3D models in the terminal

my neovim config

The Z3 Theorem Prover

Game about automating terraformation in 3D maps, ant-style.

A BSV libary providing features similar to the Stmt sub-language

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Structured concurrency in C

Haskell bindings for LLVM

elfshaker stores binary objects efficiently

RISC-V Architecture Profiles

RISC-V Profiles and Platform Specification

Synthesisable SIMT-style RISC-V GPGPU

Program to read/write from/to any location in physical memory (cloned from devmem or devmem2). See wiki.

Alogic is a Medium Level Synthesis language for digital logic that compiles swiftly into standard Verilog-2005 for implementation in ASIC or FPGA.

TAP-Y/J Test Harness

How to make logos in your README that support GitHub's new dark mode