Fix FIFO-related parameters to use DEPTH instead of ADDR_WIDTH

Signed-off-by: Alex Forencich <[email protected]>
gangsterzhou · Jul 19, 2023 · e7a2681 · e7a2681
1 parent 4a41d47
commit e7a2681
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Showing 9 changed files with 45 additions and 45 deletions.
diff --git a/rtl/i2c_master_axil.v b/rtl/i2c_master_axil.v
@@ -34,11 +34,11 @@ module i2c_master_axil #
     parameter DEFAULT_PRESCALE = 1,
     parameter FIXED_PRESCALE = 0,
     parameter CMD_FIFO = 1,
-    parameter CMD_FIFO_ADDR_WIDTH = 5,
+    parameter CMD_FIFO_DEPTH = 32,
     parameter WRITE_FIFO = 1,
-    parameter WRITE_FIFO_ADDR_WIDTH = 5,
+    parameter WRITE_FIFO_DEPTH = 32,
     parameter READ_FIFO = 1,
-    parameter READ_FIFO_ADDR_WIDTH = 5
+    parameter READ_FIFO_DEPTH = 32
 )
 (
     input  wire        clk,
@@ -372,7 +372,7 @@ generate
 
 if (CMD_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
+        .DEPTH(CMD_FIFO_DEPTH),
         .DATA_WIDTH(7+5),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(0),
@@ -416,7 +416,7 @@ end
 
 if (WRITE_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
+        .DEPTH(WRITE_FIFO_DEPTH),
         .DATA_WIDTH(8),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(1),
@@ -456,7 +456,7 @@ end
 
 if (READ_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(READ_FIFO_ADDR_WIDTH),
+        .DEPTH(READ_FIFO_DEPTH),
         .DATA_WIDTH(8),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(1),

diff --git a/rtl/i2c_master_wbs_16.v b/rtl/i2c_master_wbs_16.v
@@ -34,11 +34,11 @@ module i2c_master_wbs_16 #
     parameter DEFAULT_PRESCALE = 1,
     parameter FIXED_PRESCALE = 0,
     parameter CMD_FIFO = 1,
-    parameter CMD_FIFO_ADDR_WIDTH = 5,
+    parameter CMD_FIFO_DEPTH = 32,
     parameter WRITE_FIFO = 1,
-    parameter WRITE_FIFO_ADDR_WIDTH = 5,
+    parameter WRITE_FIFO_DEPTH = 32,
     parameter READ_FIFO = 1,
-    parameter READ_FIFO_ADDR_WIDTH = 5
+    parameter READ_FIFO_DEPTH = 32
 )
 (
     input  wire        clk,
@@ -319,7 +319,7 @@ generate
 
 if (CMD_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
+        .DEPTH(CMD_FIFO_DEPTH),
         .DATA_WIDTH(7+5),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(0),
@@ -363,7 +363,7 @@ end
 
 if (WRITE_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
+        .DEPTH(WRITE_FIFO_DEPTH),
         .DATA_WIDTH(8),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(1),
@@ -403,7 +403,7 @@ end
 
 if (READ_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(READ_FIFO_ADDR_WIDTH),
+        .DEPTH(READ_FIFO_DEPTH),
         .DATA_WIDTH(8),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(1),

diff --git a/rtl/i2c_master_wbs_8.v b/rtl/i2c_master_wbs_8.v
@@ -34,11 +34,11 @@ module i2c_master_wbs_8 #
     parameter DEFAULT_PRESCALE = 1,
     parameter FIXED_PRESCALE = 0,
     parameter CMD_FIFO = 1,
-    parameter CMD_FIFO_ADDR_WIDTH = 5,
+    parameter CMD_FIFO_DEPTH = 32,
     parameter WRITE_FIFO = 1,
-    parameter WRITE_FIFO_ADDR_WIDTH = 5,
+    parameter WRITE_FIFO_DEPTH = 32,
     parameter READ_FIFO = 1,
-    parameter READ_FIFO_ADDR_WIDTH = 5
+    parameter READ_FIFO_DEPTH = 32
 )
 (
     input  wire        clk,
@@ -307,7 +307,7 @@ generate
 
 if (CMD_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
+        .DEPTH(CMD_FIFO_DEPTH),
         .DATA_WIDTH(7+5),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(0),
@@ -351,7 +351,7 @@ end
 
 if (WRITE_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
+        .DEPTH(WRITE_FIFO_DEPTH),
         .DATA_WIDTH(8),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(1),
@@ -391,7 +391,7 @@ end
 
 if (READ_FIFO) begin
     axis_fifo #(
-        .ADDR_WIDTH(READ_FIFO_ADDR_WIDTH),
+        .DEPTH(READ_FIFO_DEPTH),
         .DATA_WIDTH(8),
         .KEEP_ENABLE(0),
         .LAST_ENABLE(1),

diff --git a/tb/test_i2c_master_axil.py b/tb/test_i2c_master_axil.py
@@ -49,11 +49,11 @@ def bench():
     DEFAULT_PRESCALE = 1
     FIXED_PRESCALE = 0
     CMD_FIFO = 1
-    CMD_FIFO_ADDR_WIDTH = 5
+    CMD_FIFO_DEPTH = 32
     WRITE_FIFO = 1
-    WRITE_FIFO_ADDR_WIDTH = 5
+    WRITE_FIFO_DEPTH = 32
     READ_FIFO = 1
-    READ_FIFO_ADDR_WIDTH = 5
+    READ_FIFO_DEPTH = 32
 
     # Inputs
     clk = Signal(bool(0))

diff --git a/tb/test_i2c_master_axil.v b/tb/test_i2c_master_axil.v
@@ -35,11 +35,11 @@ module test_i2c_master_axil;
 parameter DEFAULT_PRESCALE = 1;
 parameter FIXED_PRESCALE = 0;
 parameter CMD_FIFO = 1;
-parameter CMD_FIFO_ADDR_WIDTH = 5;
+parameter CMD_FIFO_DEPTH = 32;
 parameter WRITE_FIFO = 1;
-parameter WRITE_FIFO_ADDR_WIDTH = 5;
+parameter WRITE_FIFO_DEPTH = 32;
 parameter READ_FIFO = 1;
-parameter READ_FIFO_ADDR_WIDTH = 5;
+parameter READ_FIFO_DEPTH = 32;
 
 // Inputs
 reg clk = 0;
@@ -118,11 +118,11 @@ i2c_master_axil #(
     .DEFAULT_PRESCALE(DEFAULT_PRESCALE),
     .FIXED_PRESCALE(FIXED_PRESCALE),
     .CMD_FIFO(CMD_FIFO),
-    .CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
+    .CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
     .WRITE_FIFO(WRITE_FIFO),
-    .WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
+    .WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
     .READ_FIFO(READ_FIFO),
-    .READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
+    .READ_FIFO_DEPTH(READ_FIFO_DEPTH)
 )
 UUT (
     .clk(clk),

diff --git a/tb/test_i2c_master_wbs_16.py b/tb/test_i2c_master_wbs_16.py
@@ -49,11 +49,11 @@ def bench():
     DEFAULT_PRESCALE = 1
     FIXED_PRESCALE = 0
     CMD_FIFO = 1
-    CMD_FIFO_ADDR_WIDTH = 5
+    CMD_FIFO_DEPTH = 32
     WRITE_FIFO = 1
-    WRITE_FIFO_ADDR_WIDTH = 5
+    WRITE_FIFO_DEPTH = 32
     READ_FIFO = 1
-    READ_FIFO_ADDR_WIDTH = 5
+    READ_FIFO_DEPTH = 32
 
     # Inputs
     clk = Signal(bool(0))

diff --git a/tb/test_i2c_master_wbs_16.v b/tb/test_i2c_master_wbs_16.v
@@ -35,11 +35,11 @@ module test_i2c_master_wbs_16;
 parameter DEFAULT_PRESCALE = 1;
 parameter FIXED_PRESCALE = 0;
 parameter CMD_FIFO = 1;
-parameter CMD_FIFO_ADDR_WIDTH = 5;
+parameter CMD_FIFO_DEPTH = 32;
 parameter WRITE_FIFO = 1;
-parameter WRITE_FIFO_ADDR_WIDTH = 5;
+parameter WRITE_FIFO_DEPTH = 32;
 parameter READ_FIFO = 1;
-parameter READ_FIFO_ADDR_WIDTH = 5;
+parameter READ_FIFO_DEPTH = 32;
 
 // Inputs
 reg clk = 0;
@@ -96,11 +96,11 @@ i2c_master_wbs_16 #(
     .DEFAULT_PRESCALE(DEFAULT_PRESCALE),
     .FIXED_PRESCALE(FIXED_PRESCALE),
     .CMD_FIFO(CMD_FIFO),
-    .CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
+    .CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
     .WRITE_FIFO(WRITE_FIFO),
-    .WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
+    .WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
     .READ_FIFO(READ_FIFO),
-    .READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
+    .READ_FIFO_DEPTH(READ_FIFO_DEPTH)
 )
 UUT (
     .clk(clk),

diff --git a/tb/test_i2c_master_wbs_8.py b/tb/test_i2c_master_wbs_8.py
@@ -49,11 +49,11 @@ def bench():
     DEFAULT_PRESCALE = 1
     FIXED_PRESCALE = 0
     CMD_FIFO = 1
-    CMD_FIFO_ADDR_WIDTH = 5
+    CMD_FIFO_DEPTH = 32
     WRITE_FIFO = 1
-    WRITE_FIFO_ADDR_WIDTH = 5
+    WRITE_FIFO_DEPTH = 32
     READ_FIFO = 1
-    READ_FIFO_ADDR_WIDTH = 5
+    READ_FIFO_DEPTH = 32
 
     # Inputs
     clk = Signal(bool(0))

diff --git a/tb/test_i2c_master_wbs_8.v b/tb/test_i2c_master_wbs_8.v
@@ -35,11 +35,11 @@ module test_i2c_master_wbs_8;
 parameter DEFAULT_PRESCALE = 1;
 parameter FIXED_PRESCALE = 0;
 parameter CMD_FIFO = 1;
-parameter CMD_FIFO_ADDR_WIDTH = 5;
+parameter CMD_FIFO_DEPTH = 32;
 parameter WRITE_FIFO = 1;
-parameter WRITE_FIFO_ADDR_WIDTH = 5;
+parameter WRITE_FIFO_DEPTH = 32;
 parameter READ_FIFO = 1;
-parameter READ_FIFO_ADDR_WIDTH = 5;
+parameter READ_FIFO_DEPTH = 32;
 
 // Inputs
 reg clk = 0;
@@ -94,11 +94,11 @@ i2c_master_wbs_8 #(
     .DEFAULT_PRESCALE(DEFAULT_PRESCALE),
     .FIXED_PRESCALE(FIXED_PRESCALE),
     .CMD_FIFO(CMD_FIFO),
-    .CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
+    .CMD_FIFO_DEPTH(CMD_FIFO_DEPTH),
     .WRITE_FIFO(WRITE_FIFO),
-    .WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
+    .WRITE_FIFO_DEPTH(WRITE_FIFO_DEPTH),
     .READ_FIFO(READ_FIFO),
-    .READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
+    .READ_FIFO_DEPTH(READ_FIFO_DEPTH)
 )
 UUT (
     .clk(clk),