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Technically-oriented PDF Collection (Papers, Specs, Decks, Manuals, etc)
HTML UpdatedAug 2, 2023 -
dbt-rules Public
Forked from daedaleanai/dbt-rulesRules for the DBT build system
Go MIT License UpdatedJun 20, 2022 -
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ibex Public
Forked from lowRISC/ibexIbex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
SystemVerilog Apache License 2.0 UpdatedMay 3, 2021 -
riscv-extension-interface Public
Forked from openhwgroup/core-v-xifSystemVerilog UpdatedApr 28, 2021 -
pulp_cluster Public
Forked from pulp-platform/pulp_clusterThe multi-core cluster of a PULP system.
SystemVerilog Other UpdatedJan 14, 2021 -
pulp Public
Forked from pulp-platform/pulpThis is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
SystemVerilog Other UpdatedDec 30, 2020 -
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pulp-riscv-gcc Public
Forked from gtagliavini/pulp-riscv-gccC GNU General Public License v2.0 UpdatedNov 26, 2020 -
cv32e40p Public
Forked from openhwgroup/cv32e40pCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
SystemVerilog Other UpdatedNov 11, 2020 -
cva6 Public
Forked from openhwgroup/cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SystemVerilog Other UpdatedNov 10, 2020 -
riscv-bitmanip Public
Forked from riscv/riscv-bitmanipWorking draft of the proposed RISC-V Bitmanipulation extension
Assembly UpdatedApr 22, 2020 -
pulp-rt-examples Public
Forked from pulp-platform/pulp-rt-examplesC Apache License 2.0 UpdatedJan 13, 2020 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedDec 15, 2019 -