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Compact and Efficient RISC-V RV32I[MAFC] emulator

C 418 101 Updated Dec 28, 2024

ePIC (Embedded PIC) example: kernel and relocatable loadable app

C 11 4 Updated Oct 27, 2023

Instruction Set Generator initially contributed by Futurewei

C++ 268 61 Updated Oct 17, 2023

Build your hardware, easily!

C 3,085 577 Updated Dec 21, 2024

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Bluespec 24 8 Updated Dec 20, 2024

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,425 557 Updated Dec 20, 2024

A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

C 91 8 Updated Sep 26, 2022

This instruction will teach you how to run a linux kernel with riscv emulators like Spike or QEMU from scratch

5 Updated May 26, 2020

Notes for software, network, Linux and so on.

99 58 Updated Apr 21, 2020

RISC-V Bare Metal Boot Loader.

C 8 3 Updated Sep 29, 2016

Documentation for RISC-V Spike

98 11 Updated Oct 18, 2018

RISCV full system support on gem5 related files live here

Python 17 Updated Jan 24, 2022

Updated version of the XUP Workshops

HTML 18 21 Updated Aug 10, 2018

RISC-V Torture Test

Scala 170 48 Updated Jul 11, 2024

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Assembly 543 43 Updated Jan 4, 2024

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala 1,698 665 Updated Dec 27, 2024

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,185 767 Updated Jun 27, 2024

LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.

Verilog 32 7 Updated Jan 6, 2023
SystemVerilog 25 9 Updated Aug 8, 2020

Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare

275 94 Updated Mar 27, 2023

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

SystemVerilog 289 200 Updated Dec 24, 2024

My first simple cpu based on risc-v

Verilog 5 Updated Mar 20, 2023

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,643 1,019 Updated Mar 24, 2021

A very simple and easy to understand RISC-V core.

C 1,136 191 Updated Nov 9, 2023

RISC-V Disassembler

C 8 2 Updated Apr 18, 2021

NVIDIA Linux open GPU kernel module source

C 15,347 1,308 Updated Dec 17, 2024

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SystemVerilog 863 95 Updated Nov 22, 2024

Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler.

C 11 1 Updated Sep 29, 2022

Fork of http://sourceforge.net/projects/mjpg-streamer/

C 3,042 1,231 Updated Aug 8, 2024

A tiny RISC-V instruction decoder and instruction set simulator

Python 12 Updated Jun 15, 2024
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