Stars
Compact and Efficient RISC-V RV32I[MAFC] emulator
ePIC (Embedded PIC) example: kernel and relocatable loadable app
Instruction Set Generator initially contributed by Futurewei
CTSRD-CHERI / Toooba
Forked from bluespec/TooobaRISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
This instruction will teach you how to run a linux kernel with riscv emulators like Spike or QEMU from scratch
RISCV full system support on gem5 related files live here
Updated version of the XUP Workshops
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.
Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
A very simple and easy to understand RISC-V core.
NVIDIA Linux open GPU kernel module source
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler.
Fork of http://sourceforge.net/projects/mjpg-streamer/
A tiny RISC-V instruction decoder and instruction set simulator