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SystemVerilog 4 Updated Nov 11, 2019

Code of the Entangling Instruction Prefetcher

C++ 8 3 Updated Dec 7, 2023

Random instruction generator for RISC-V processor verification

Python 1,042 332 Updated Aug 29, 2024

The official repository for the gem5 computer-system architecture simulator.

C++ 1,759 1,273 Updated Dec 27, 2024

Open-source high-performance RISC-V processor

Scala 4,989 674 Updated Dec 27, 2024

NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching

C 920 195 Updated Oct 20, 2024