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Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis

C++ 22 2 Updated Jul 29, 2022

Fast Floating Point Operators for High Level Synthesis

C++ 20 4 Updated Feb 23, 2023

DUTH RISC-V Microprocessor

SystemVerilog 19 7 Updated Dec 4, 2024

DUTH RISC-V Superscalar Microprocessor

SystemVerilog 30 10 Updated Oct 23, 2024

Vector processor for RISC-V vector ISA

SystemVerilog 113 25 Updated Oct 19, 2020

HLS for Networks-on-Chip

C++ 33 5 Updated Feb 18, 2021